VHDL-FPGA-Verilog List Page 1197

VHDL-FPGA-Verilog list

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ch5 Downloaded：0: technology of vhdl；u5
Date : 2025-08-22 Size : 783kb User : 兆斌
ch6 Downloaded：0: technology of vhdl；u6
Date : 2025-08-22 Size : 3.61mb User : 兆斌
loop_with_mac Downloaded：0: configuration of 88e1111 and mac ip
Date : 2025-08-22 Size : 99kb User : 葛
key_smiao Downloaded：0: the matrix keyboard VHDL language acquisition program, debug through
Date : 2025-08-22 Size : 1kb User : lh
SDRAM Downloaded：0: For some VHDL code with XilinxSC1500 Control SDRAM. Control SDRAM Each clock output address where a data.
Date : 2025-08-22 Size : 4kb User : xiaozhiji
hyalite3 Downloaded：0: Digital clock 1, with hours, minutes, seconds count display features cyclic timing twenty-four hours. 2, has cleared, adjust the hours, minutes function. 3, with the pattern of the whole point of time while the LED light
Date : 2025-08-22 Size : 14kb User : 童巧英
hyalite4 Downloaded：0: The four DIP the switch provides 8421BCD yards after decoding circuit 8 digital tube-shaped display drive signal a, b, c, d, e, f, g.
Date : 2025-08-22 Size : 13kb User : 童巧英
hyalite5 Downloaded：0: Design a rounding discriminating circuit, its input 8421BCD code required when the input is greater than or equal to 5, the output of the discriminating circuit 1, and 0 otherwise
Date : 2025-08-22 Size : 18kb User : 童巧英
adaptive_lms_equalizer_latest.tar Downloaded：0: It is the code for Adaptive Equalizer LMS Algorithm
Date : 2025-08-22 Size : 25kb User : Adarsh
src_adc Downloaded：0: The AD acquisition, DDC, FIRD etc. filtering procedures, adc lvds interface
Date : 2025-08-22 Size : 79kb User : ww
shr_spi3.tar Downloaded：0: SPI3 interface under cadence， include the source file and the simulation file
Date : 2025-08-22 Size : 29kb User : 安得
Dny_LCD Downloaded：0: LCD verilog codes for labrotuary
Date : 2025-08-22 Size : 2.07mb User : Akbas

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