VHDL-FPGA-Verilog List Page 115

VHDL-FPGA-Verilog list

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mustafaokanyolcakar Downloaded：0: divide-and-conquer algorithm for finding the position of the largest element in an array
Date : 2025-05-18 Size : 927kb User : okanijerya
sim Downloaded：0: Debug bcm5396, write and read the internal register function. Functional validation can be used
Date : 2025-05-18 Size : 2kb User : qoduliag
nokia ring tone RTLL Downloaded：0: Nokia ringtones 8051
Date : 2025-05-18 Size : 15kb User : CarlosORION
yii-account-module-master (1) Downloaded：0: mkjhkjh kjhjkhjkhk kjhkjh kjhkj
Date : 2025-05-18 Size : 15kb User : attari
uart_latest.tar Downloaded：0: UART's VHDL modeling code is a standard IP core
Date : 2025-05-18 Size : 9kb User : scenic_lee
HardwareDesignAndModeling Downloaded：0: instruction vhdl persian
Date : 2025-05-18 Size : 2.06mb User : salar395
xsym Downloaded：0: The digital tube displays the source code of the beginner. Hope to pass through
Date : 2025-05-18 Size : 112kb User : 额还吐
key_led Downloaded：0: led ctrl it's easy
Date : 2025-05-18 Size : 202kb User : 醉枫染墨
clock Downloaded：0: Digital clock, designed in VHDL language, can adjust the time, the whole bell ring
Date : 2025-05-18 Size : 134kb User : liujhliujp81
lab1 Downloaded：0: Test the passing FPGA flow lamp on vivado
Date : 2025-05-18 Size : 2kb User : 小晰
lab3 Downloaded：0: FPGA frequency divider tested on vivado
Date : 2025-05-18 Size : 3kb User : 小晰
lab4 Downloaded：0: Test the FPGA filter passed on vivado
Date : 2025-05-18 Size : 4kb User : 小晰

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