VHDL-FPGA-Verilog List Page 1133

VHDL-FPGA-Verilog list

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cpu Downloaded：0: This my curriculum design. Micro-program control CPU can read instructions from the RAM and executed. Contains the MBR, MAR, IR, BR, ALU, PC and other functional components, can be realized subtraction multiplication, lo
Date : 2025-08-21 Size : 4.46mb User : cxl
chuankoushoufa Downloaded：0: Receive code: Sampling frequency of the received data: 16X9600HZ Receive coding ideas: Analyzing first start bit, the start bit is "1" state when no data is transmitted, when the data start bit is "0". Because the sampli
Date : 2025-08-21 Size : 84kb User : ran feng
VHDL Downloaded：2: VHDL the primary programming examples: dynamic scanning display program, the divider design process, the 8-bit shift register, BCD counter design (any hex), and so on.
Date : 2025-08-21 Size : 11kb User : 罗梵
16QAM Downloaded：0: Using a Lookup Table the 16QAM modulation source code using Verilog language
Date : 2025-08-21 Size : 4kb User :
HDB3_ Downloaded：0: HDB3 encoder using Verilog language.
Date : 2025-08-21 Size : 2kb User :
Nios2 Downloaded：0: Based on the DE2 board, to achieve LCD display.
Date : 2025-08-21 Size : 1.71mb User : ZhaoXia
fuzaliushuideng Downloaded：0: Simple light water program, simple and complex, there are for FPGA beginners reference only.
Date : 2025-08-21 Size : 151kb User : 梁文斌
mod_4psk Downloaded：0: Using VHDL language achieve 4PSK modulation source code
Date : 2025-08-21 Size : 1kb User :
demod_4psk Downloaded：0: Using VHDL realize 4PSK demodulation source code
Date : 2025-08-21 Size : 1kb User :
sorter Downloaded：0: Sequential n-deep w-wide unsigned sorter.
Date : 2025-08-21 Size : 2kb User : thomz
sorter_tb Downloaded：0: Test bench for Sequential n-deep w-wide unsigned sorter
Date : 2025-08-21 Size : 2kb User : thomz
Median-Module Downloaded：0: Median Module VHDL code
Date : 2025-08-21 Size : 1kb User : thomz

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