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  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-05-01
  • Size : 1.71mb
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  • Author :Zha****
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Introduction - If you have any usage issues, please Google them yourself
Based on the DE2 board, to achieve LCD display.
Packet file list
(Preview for download)


Nios2\.sopc_builder\install.ptf
.....\.............\install2.ptf
.....\.............\preferences.xml
.....\altpllpll.cmp
.....\altpllpll.inc
.....\altpllpll.ppf
.....\altpllpll.vhd
.....\altpllpll_1.ppf
.....\altpllpll_1.vhd
.....\avalon_pwm.v
.....\avalon_pwm.vhd
.....\button_pio.vhd
.....\clock_0.vhd
.....\cpu.ocp
.....\cpu.vhd
.....\cpu.vho
.....\cpu_ic_tag_ram.mif
.....\cpu_jtag_debug_module.vhd
.....\cpu_jtag_debug_module_wrapper.vhd
.....\cpu_mult_cell.vhd
.....\cpu_ociram_default_contents.mif
.....\cpu_rf_ram_a.mif
.....\cpu_rf_ram_b.mif
.....\cpu_test_bench.vhd
.....\db\altsyncram_9tl1.tdf
.....\..\altsyncram_cub1.tdf
.....\..\altsyncram_e502.tdf
.....\..\altsyncram_gge1.tdf
.....\..\altsyncram_k1l1.tdf
.....\..\altsyncram_l6e1.tdf
.....\..\altsyncram_lo31.tdf
.....\..\altsyncram_m6e1.tdf
.....\..\altsyncram_t072.tdf
.....\..\a_dpfifo_8t21.tdf
.....\..\a_fefifo_7cf.tdf
.....\..\cntr_fjb.tdf
.....\..\cntr_rj7.tdf
.....\..\DE2Project.db_info
.....\..\DE2Project.eco.cdb
.....\..\DE2Project.sld_design_entry.sci
.....\..\decode_aoi.tdf
.....\..\ded_mult_2o81.tdf
.....\..\dffpipe_93c.tdf
.....\..\dpram_5h21.tdf
.....\..\mult_add_4cr2.tdf
.....\..\mult_add_6cr2.tdf
.....\..\prev_cmp_DE2Project.asm.qmsg
.....\..\prev_cmp_DE2Project.fit.qmsg
.....\..\prev_cmp_DE2Project.map.qmsg
.....\..\prev_cmp_DE2Project.qmsg
.....\..\prev_cmp_DE2Project.tan.qmsg
.....\..\scfifo_1n21.tdf
.....\DE2Project.asm.rpt
.....\DE2Project.bdf
.....\DE2Project.cdf
.....\DE2Project.done
.....\DE2Project.fit.rpt
.....\DE2Project.fit.smsg
.....\DE2Project.fit.summary
.....\DE2Project.flow.rpt
.....\DE2Project.jdi
.....\DE2Project.map.rpt
.....\DE2Project.map.summary
.....\DE2Project.pin
.....\DE2Project.pof
.....\DE2Project.qpf
.....\DE2Project.qsf
.....\DE2Project.qws
.....\DE2Project.sof
.....\DE2Project.tan.rpt
.....\DE2Project.tan.summary
.....\DE2Project_assignment_defaults.qdf
.....\epcs_controller.vhd
.....\epcs_controller_boot_rom.hex
.....\high_res_timer.vhd
.....\jtag_uart.vhd
.....\lcd.vhd
.....\led_green.vhd
.....\NIOSii.bsf
.....\NIOSii.ptf
.....\NIOSii.ptf.bak
.....\NIOSii.ptf.pre_generation_ptf
.....\NIOSii.qip
.....\NIOSii.sopc
.....\NIOSii.vhd
.....\NIOSii_generation_script
.....\NIOSii_log.txt
.....\NIOSii_setup_quartus.tcl
.....\........im\atail-f.pl
.....\..........\cpu_ic_tag_ram.dat
.....\..........\cpu_ic_tag_ram.hex
.....\..........\cpu_ociram_default_contents.dat
.....\..........\cpu_ociram_default_contents.hex
.....\..........\cpu_rf_ram_a.dat
.....\..........\cpu_rf_ram_a.hex
.....\..........\cpu_rf_ram_b.dat
.....\..........\cpu_rf_ram_b.hex
.....\..........\create_NIOSii_project.do
.....\..........\epcs_controller_boot_rom.dat
.....\..........\epcs_controller_boot_rom.hex
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