[Streaming Mpeg4] msa

Description: Scrambler and Descrambling codec: DVB_S data for Canada around the
Platform: | Size: 99140 | Author: 长空 | Hits:

[Other resource] binarytree

Description: 1) list for binary storage structure, to write the establishment of binary tree, the first sequence (in sequence, after the sequence) binary tree traversal, and the total number of tree nodes, a few leaves, tree height a
Platform: | Size: 22546 | Author: 姜华 | Hits:

[Technology Management] pt100

Description: PT100 measurement circuit and measurement method for high-precision design and development
Platform: | Size: 7509 | Author: 王涛 | Hits:

[Windows Develop] Polynomial

Description: The use of chain store realize one of the following polynomial operation: (1), the basic requirements: the realization of polynomial addition, subtraction, derivation. (2), the realization of polynomial multiplication
Platform: | Size: 16859 | Author: 姜华 | Hits:

[Other resource] MSP430Timer_B

Description: MSP430
Platform: | Size: 22002 | Author: 王涛 | Hits:

[Other resource] interleave

Description: Data interleaver verilog HDL source file
Platform: | Size: 100606 | Author: 长空 | Hits:

[Other resource] linlist

Description: Create a sequence table: the output sequence table: the order of the output of various elements insertion sequence table: Insert in the designated location element delete the order form: delete the specified location in
Platform: | Size: 29664 | Author: 姜华 | Hits:

[Other resource] syn_frame

Description: Frame Synchronization Verilog HDL source code to achieve synchronization receiver
Platform: | Size: 77248 | Author: 长空 | Hits:

[Other resource] wrl_model

Description: To look at a few simple wrl model, you need Come under
Platform: | Size: 2575444 | Author: lvkun | Hits:

[assembly language] dd

Description: Many things in this program can be configured in the data section Configurable square size, color, interface location, use of keys, each square model shape You can configure the shape of each square model to change, and
Platform: | Size: 4664 | Author: 张磊 | Hits:

[Other resource] CRC

Description: Cyclic Redundancy Check realize Verilog source code
Platform: | Size: 367681 | Author: 长空 | Hits:

[Other resource] add

Description: Used realize adder VerilogHDL Le Hua domain adder
Platform: | Size: 194077 | Author: 长空 | Hits: