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[Other resource] watch

Description: 用FPGA实现带马表日历的电子表，verilog代码。
Platform: | Size: 3705 | Author: nothing | Hits:

[VHDL-FPGA-Verilog] 74138_0

Description: 这是老师给的3—8译码器的源程序，自己刚才调试过了，真的成功了，哈哈……，有需要就看看吧-This the teacher for the 3-8 decoder source, have their own testing before, and really successful, ha ha ... there is a need to watch it!
Platform: | Size: 1024 | Author: wenjun | Hits:

[VHDL-FPGA-Verilog] watch

Description: 用FPGA实现带马表日历的电子表，verilog代码。-Using FPGA to achieve with digital watches stopwatch calendar, verilog code.
Platform: | Size: 3072 | Author: nothing | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[Other] watch

Description: 基于quartus II软件 用verilog 语言描述的一个秒表-quartus II verilog
Platform: | Size: 105472 | Author: xu | Hits:

[VHDL-FPGA-Verilog] watch

Description: 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
Platform: | Size: 388096 | Author: 潘萌 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
Platform: | Size: 2747392 | Author: 曹丽娜 | Hits:

[Software Engineering] Watch

Description: Design Watch with set time by Verilog for kit DE2
Platform: | Size: 800768 | Author: Gau | Hits:

[VHDL-FPGA-Verilog] DigitalWatch

Description: Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
Platform: | Size: 15360 | Author: minh | Hits:

[VHDL-FPGA-Verilog] foundatonise

Description: WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256 -6) -WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256-6)
Platform: | Size: 123904 | Author: SEEDSTART | Hits:

[VHDL-FPGA-Verilog] watch(2)

Description: digital watch : verilog source code
Platform: | Size: 399360 | Author: hanjaeyoung | Hits:

[VHDL-FPGA-Verilog] watch

Description: 懂哥作品 用verilog编写的，我没试验呢开发板没有-verilog watch made by dongge
Platform: | Size: 36864 | Author: 张专 | Hits:

[VHDL-FPGA-Verilog] FPGA_A.Thien

Description: stop – watch (verilog)
Platform: | Size: 24428544 | Author: viet | Hits:

[VHDL-FPGA-Verilog] watch

Description: verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
Platform: | Size: 1516544 | Author: 孙祥龙 | Hits:

[VHDL-FPGA-Verilog] clock-design-verilog-Fpga

Description: verilog设计的计时表，数字电路设计，FPGA-using verilog design watch, digital circuit design, FPGA
Platform: | Size: 1525760 | Author: Nee | Hits:

[VHDL-FPGA-Verilog] digital_watch

Description: Verilog code of digital watch
Platform: | Size: 12288 | Author: M. Usman | Hits:

[Game Program] stop-watch

Description: stopwatch with verilog it counts up and reset
Platform: | Size: 138240 | Author: haemoon | Hits:

[Software Engineering] final_lab5

Description: Verilog code for stop watch
Platform: | Size: 3401728 | Author: wenyuan | Hits:

[Other] watch_dog

Description: verilog实现watch dog看门狗功能。(watch Implement watch dog function.)
Platform: | Size: 1024 | Author: kevin_li | Hits:

[VHDL-FPGA-Verilog] verilog-stopwatch-master

Description: verilog stop watch code for end user
Platform: | Size: 10240 | Author: nira | Hits:
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