Welcome![Sign In][Sign Up]
Location:
Search - vhdl_clock

Search list

[File OperateVHDL_clock

Description: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Platform: | Size: 105273 | Author: lianbin | Hits:

[Other resourcevhdl_clock

Description: VHDL实现数字时钟,利用数码管和CPLD 设计的计数器实现一个数字时钟,可以显示小时,分钟,秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 324949 | Author: 赵海东 | Hits:

[Other resourceVHDL_clock

Description: 数字钟 实现时、分、秒的显示和定时闹铃、整点报时等功能。
Platform: | Size: 9409 | Author: 吴称光 | Hits:

[File FormatVHDL_clock

Description: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Platform: | Size: 105472 | Author: lianbin | Hits:

[VHDL-FPGA-Verilogvhdl_clock

Description: VHDL实现数字时钟,利用数码管和CPLD 设计的计数器实现一个数字时钟,可以显示小时,分钟,秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 324608 | Author: 赵海东 | Hits:

[source in ebookVHDL_clock

Description: 数字钟 实现时、分、秒的显示和定时闹铃、整点报时等功能。-Realize digital clock hour, minute, second display and timing alarm, the whole point timekeeping functions.
Platform: | Size: 9216 | Author: 吴称光 | Hits:

[VHDL-FPGA-Verilogvhdl_clock

Description: VHDL数字钟设计程序 设计要求 基本要求: 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响);-VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring)
Platform: | Size: 7168 | Author: 孙超 | Hits:

[VHDL-FPGA-VerilogVHDL_clock

Description: 用VHDL写的数字电子钟的实例,采用的是altera的FPGA芯片-VHDL examples of digital electronic clock
Platform: | Size: 6144 | Author: zhangwei | Hits:

[VHDL-FPGA-VerilogVHDL_clock

Description: VHDL数字钟设计程序 设计要求 基本要求: 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响);--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -
Platform: | Size: 71680 | Author: 苹果熊 | Hits:

[VHDL-FPGA-VerilogVHDL_clock

Description: 关于电子数字钟得FPGA实现,上传来分享一下-Electronic digital clock was on the FPGA, upload to share with you
Platform: | Size: 2754560 | Author: 甘超 | Hits:

[VHDL-FPGA-VerilogVHDL_clock

Description: VHDL电子钟,课程设计,时间可调,有闹钟,大小月,闰年,整点报时-a clock which is write in VHDL language
Platform: | Size: 39936 | Author: 王宇 | Hits:

[VHDL-FPGA-VerilogVHDL_clock

Description: 运用VHDL写的时钟控制程序,状态机,时钟分频,频率变换。-VHDL clock
Platform: | Size: 12178432 | Author: YH | Hits:

CodeBus www.codebus.net