Search - vhdl 9999

[Other resource] frequency

Description: 这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。
Platform: | Size: 1243027 | Author: yato_logo | Hits:

[VHDL-FPGA-Verilog] 9999counter

Description: ——9999计数器模块　四输出设计要求频率计为四段显示，故计数器采用0~~9999计数，可以很好的利用数码管，以及增加频率计的精确度。模块内包含俩个进程，一为计数进程，二为时基信号控制计数模块数据输出进程。
Platform: | Size: 1024 | Author: 张伯伦 | Hits:

Description: 这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。-This procedure is based on the principle of frequency measurement accuracy, such as the frequency meter, using VHDL language, frequency measurement range 1 ~ 9999 with four decimal places with the frequency of the digital display and has a super-range, less range prompts.
Platform: | Size: 1243136 | Author: yato_logo | Hits:

[VHDL-FPGA-Verilog] seg73

Description: 递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. -- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-
Platform: | Size: 201728 | Author: | Hits:

[VHDL-FPGA-Verilog] 9999jishu

Description: VHDL语言编程，7段共阴数码管显示（四个数码管）其中使用的是进程语句，使用MAX+puls编程。-VHDL language programming, a total of 7 negative digital display (four digits) which is used in the process of language, the use of MAX+ puls programming.
Platform: | Size: 1024 | Author: liliang | Hits:

[VHDL-FPGA-Verilog] counter

Description: 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
Platform: | Size: 131072 | Author: flyingwings | Hits:

[VHDL-FPGA-Verilog] all

Description: 利用VHDL程式達到上數9999 並且有遮沒+防彈跳功能，是個很好又實際的程式。-Reached on the use of VHDL program and the number of 9999 did not cover+ anti-bounce function is a very good and practical programs.
Platform: | Size: 508928 | Author: 黃嘉偉 | Hits:

[VHDL-FPGA-Verilog] count

Description: VHDL语言编写的计数器程序，实现1到9999计数，并动态扫描显示，带清零和暂停功能，课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
Platform: | Size: 97280 | Author: Archimedes Lu | Hits:

[VHDL-FPGA-Verilog] jishuqi

Description: 计数到9999，然后显示 VHDL语言编写-Count to 9999, and then display the VHDL language
Platform: | Size: 464896 | Author: 尚勇 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 这是一个从零计数到9999在归零的vhdl程序，程序不复杂，对于理解分频原理，数码管显示原理有很大的帮助-This is a count from zero to zero in the vhdl program in 9999, the program is not complicated, the principle for understanding the frequency, digital display of great help to the principle
Platform: | Size: 1024 | Author: 王冰 | Hits:

[VHDL-FPGA-Verilog] qiduanshumaguandongtaixianshi0000-9999

Description: 七段数码管动态显示采用vhdl语言设计编译已通过-Seven-Segment LED dynamic display design using vhdl language compiler has passed
Platform: | Size: 425984 | Author: 王冠 | Hits:

[VHDL-FPGA-Verilog] VHDL-the-count

Description: 利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数-Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
Platform: | Size: 648192 | Author: sunhuiping | Hits:

[VHDL-FPGA-Verilog] LED_0000_9999

Description: 7段数码管动态显示0000-9999,vhdl语言-7-segment LED dynamic display of 0000-9999, the VHDL language
Platform: | Size: 1024 | Author: 黄鹏 | Hits:

[VHDL-FPGA-Verilog] demo3-seg2_vhdl

Description: ep1c3-seg1_vhdl,７段数码管实验２：递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. 设计了一个4位十进制计数器，并用数码管显示当前计数值-ep1c3-seg1 vhdl, 7-segment LED Experiment 2: incrementally on four digital display counts up 0000-0001-> 0002 ...... ..9999 ... ... .0001 ... of 0000h. - Design of a 4-digit decimal counter, and with a digital display of the current count value
Platform: | Size: 171008 | Author: davidobt | Hits:

[VHDL-FPGA-Verilog] DTCNT9999

Description: 9999计数器，源代码用VHDL进行书写，设计中有计数模块，动态扫描模块，动态显示模块。书写规范，易于理解。-9999 counters, source code written in VHDL are, in the design of counting module, dynamic scanning module, dynamic display module.
Platform: | Size: 3612672 | Author: chen | Hits:

[VHDL-FPGA-Verilog] count

Description: 本实验利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数。 SW0 为复位开关。当开关拨至高点平时，计数器归0，当开关拨至低电平时，计数器开始计数。该电路包括分频电路，计数器电路，二进制转BCD 码电路和数码管显示电路。-This experiment uses VHDL hardware description language to design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger Clock, the counter counts up, and the use of digital tube display, when the count to 9999, 0 to re-count. SW0 is the reset switch. When the switch to the high point of ping, the counter to 0, when the switch to low, the counter began to count. The circuit includes a frequency dividing circuit, a counter circuit, a binary-to-BCD code circuit and a digital tube display circuit.
Platform: | Size: 475136 | Author: panda | Hits:

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[Other resource] frequency

[VHDL-FPGA-Verilog] 9999counter

[VHDL-FPGA-Verilog] frequency

[VHDL-FPGA-Verilog] seg73

[VHDL-FPGA-Verilog] 9999jishu

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] all

[VHDL-FPGA-Verilog] count

[VHDL-FPGA-Verilog] jishuqi

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] qiduanshumaguandongtaixianshi0000-9999

[VHDL-FPGA-Verilog] VHDL-the-count

[VHDL-FPGA-Verilog] LED_0000_9999

[VHDL-FPGA-Verilog] demo3-seg2_vhdl

[VHDL-FPGA-Verilog] DTCNT9999

[VHDL-FPGA-Verilog] count

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