Description: Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
- [Ripple_Carry_counter] - Ripple Carry Counter. the synchronous ve
- [counter] - Count based on VHDL code for FPGA chips
- [leds] - xilinx SPARTAN3E led under the seven-seg
- [XDSP] - Xilinx DSP Design with Matlab binding as
- [verilog] - Chapter 1 of the EDA Design and Verilog
File list (Check if you may need any files):
counter.doc
counter.v
counter.v.bak
counter.xml
counter_0to9999.v
counter_0to9999.v.bak
counter_divider.bak
counter_divider.v
counter_divider.v.bak
counter_tb.v
counter_tb.v.bak
modelsim.ini
sevenseg_display.v
sevenseg_display.v.bak
seven_control.v
seven_control.v.bak
transcript
vsim.wlf
work
....\counter
....\.......\verilog.asm
....\.......\_primary.dat
....\.......\_primary.vhd
....\counter_0to9999
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_divider
....\...............\verilog.asm
....\...............\_primary.dat
....\...............\_primary.vhd
....\counter_tb
....\..........\verilog.asm
....\..........\_primary.dat
....\..........\_primary.vhd
....\sevenseg_display
....\................\verilog.asm
....\................\_primary.dat
....\................\_primary.vhd
....\seven_contrl
....\............\verilog.asm
....\............\_primary.dat
....\............\_primary.vhd
....\_info
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