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[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[Com Port] rec

Description: uart串口通信程序 用VERILOG HDL　编写　可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:

[Software Engineering] xapp341

Description: verilog uart for spartan 3 fpga, its great
Platform: | Size: 21504 | Author: kashif | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[Other Embeded program] uart

Description: fpga 串行口 接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
Platform: | Size: 371712 | Author: james | Hits:

[Com Port] UART

Description: 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!
Platform: | Size: 2269184 | Author: Kerwin | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] uart1

Description: RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
Platform: | Size: 237568 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
Platform: | Size: 64512 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
Platform: | Size: 1435648 | Author: 冰色火焰 | Hits:

[VHDL-FPGA-Verilog] UART

Description: FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
Platform: | Size: 276480 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
Platform: | Size: 709632 | Author: xiong | Hits:

[Com Port] FPGA-RS232-verilog

Description: fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
Platform: | Size: 500736 | Author: yvaine | Hits:

[VHDL-FPGA-Verilog] UART

Description: xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
Platform: | Size: 10240 | Author: 雪尘 | Hits:

[VHDL-FPGA-Verilog] my_uart1_VERILOG_using-PLL

Description: Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using PLL
Platform: | Size: 506880 | Author: 林端 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
Platform: | Size: 308224 | Author: 怪了个乖 | Hits:

[VHDL-FPGA-Verilog] uart

Description: FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
Platform: | Size: 117760 | Author: gq_zhou | Hits:
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