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[assembly language] EEPROMpresentation

Description: 利用拨码开关为可编程器件输入读写命令和相应的地址、数据，8051读入可编程器件设定的命令字并根据可编程器件的设置进行读写操作，读出来的数据通过P0输出给可编程器件，并由可编程器件控制七段数码管显示。(Verilog+单片机)-DIP switch for the use of programmable devices to read and write command input and the corresponding address, data, read into the programmable device 8051 set the word order and in accordance with programmable device settings for read and write operations, read out the data through P0 output to the programmable device, programmable device controlled by the Seven-Segment LED display. (Verilog+ Singlechip)
Platform: | Size: 3072 | Author: 辛颖 | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[SCM] 16bit_display8bitLED

Description: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results.
Platform: | Size: 7168 | Author: 王媛媛 | Hits:

[SCM] shumaguan

Description: 七段数码管显示程序，用Verilog语言编写，程序运行完全没有问题。-Seven-Segment LED display program, with the Verilog language, the program is running is no problem.
Platform: | Size: 415744 | Author: 韩瑞 | Hits:

[VHDL-FPGA-Verilog] sn7448

Description: verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
Platform: | Size: 1024 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some of the I2C bus function, and can be carried out through the bus, read and write operations on the AT24C02. To read and write eeprom in order to facilitate observation of the results, we will read and write data simultaneously displayed in the seven-segment digital tube, and set read and write data from 0 to 255 in cycles, so that can be easily compared.
Platform: | Size: 8192 | Author: andy | Hits:

[VHDL-FPGA-Verilog] Sevenseg

Description: verilog code for a decoder that converts bcd to seven segment leds
Platform: | Size: 23552 | Author: z | Hits:

[VHDL-FPGA-Verilog] calculator

Description: 课设一个，又臭又长，是一个用verilog编写的计算器，对应革新科技的某个sopc开发平台，键盘会扫描，七段二极管会译码且是并行输出，上传的是整个工程，在该开发平台上基本正常，主程序段编写的较为幼稚，希望大家多多扔玉。注：主程序段预计做八位计算器，后来因为实验平台只有六个数码管无奈之下后两位没接，主程序中的ac有问题，在开发平台上没效果，压缩包里的图是主程序在quartus下的仿真图，开发环境是quartus，不知应选哪项。最后：初次上传欢迎指正 -Set up a class, but also smell and long, is a calculator written using verilog, corresponding to a sopc innovative science and technology development platform, the keyboard scan, seven-segment LED will be parallel decode and output, upload the entire project, In the normal development platform, the main program segment written in a more naive, I hope Members can throw jade. Note: The main program segment is expected to make eight calculators, and later because the experimental platform is only six digits after the two did not desperation then, the main program of the ac problems did not result in the development of platforms, compressed bag of Figure is the main program under the simulation diagram in quartus, development environment is quartus, do not know which of the election. Last: initial upload please correct me
Platform: | Size: 10809344 | Author: raven | Hits:

[Other] seven_seg_decoder

Description: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no.
Platform: | Size: 1024 | Author: hassan | Hits:

[Other] binary_to_bcd

Description: this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder-this is a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder
Platform: | Size: 1024 | Author: hassan | Hits:

[assembly language] seg7_counter

Description: 這是一個提供上下數的七段顯示器之verilog的程式。透過此程式可簡易的學習如何撰寫程式來控制七段顯示器。-This is a seven-segment display to provide the upper and lower number of verilog program. Through this program can be simple to learn how to write programs to control the seven-segment display.
Platform: | Size: 1024 | Author: LAB | Hits:

[VHDL-FPGA-Verilog] SEG7_Timer

Description: 七段数码管时钟显示的verilog程序，开发环境quartusII7.0-Seven-segment digital tube display clock verilog program development environment quartusII7.0
Platform: | Size: 9036800 | Author: 杜征宇 | Hits:

[VHDL-FPGA-Verilog] LEDdecode

Description: 由verilog相应的LED显示的七段码的相应的译码模块-By the corresponding verilog seven segment LED displays the corresponding code decoding module
Platform: | Size: 1024 | Author: 不是人 | Hits:

[VHDL-FPGA-Verilog] digital_7

Description: Verilog七段数码管显示控制程序，已经在实验板上测试通过。-Verilog seven-segment LED display control program, the board has been tested in the experiment.
Platform: | Size: 445440 | Author: 吴平 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-bit successive-carry adder, 16-bit look-ahead bit adder, 16-bit adder cascade, choose a multi-channel four-level design, seven-segment decoder gate-level design
Platform: | Size: 1326080 | Author: 城管111 | Hits:

[Other] Verilog

Description: 用Verilog语言编写的多功能数字钟，用七段显示时钟-Verilog language, multi-function digital clock clock, seven-segment display
Platform: | Size: 140288 | Author: bingye | Hits:

[VHDL-FPGA-Verilog] test1

Description: 七段译码器的verilog语言程序，功能由七根二极管来显示0到9数字的东西，就是显示器(seven-segment decoder)
Platform: | Size: 45056 | Author: LdF!!! | Hits:

[VHDL-FPGA-Verilog] top1

Description: 七段数码管译码器，可显示0~9共10个字符。(Seven segment digital decoder, 0~9 can display a total of 10 characters.)
Platform: | Size: 442368 | Author: Stella\ | Hits:

[Embeded-SCM Develop] 红外接收解码

Description: 红外接收解码 工程说明 本案例实现了编码格式为“引导码+地址码+数据码+数据反码”的红外发送数据进行接收和解码，并将收到的数据显示到七段译码器上。 案例补充说明 在实际的产品设计或业余电子制作中，编码芯片并一定能完成要求的功能，这时就需要了解所使用的编码芯片到底是如何编码的。只有知道编码方式，我们才可以使用单片机或数字电路去定制解码方案。(Infrared receiving and decoding Engineering description In this case the encoding format for infrared sending data to guide the code and address code + data + code data complement "is received and decoded, and display the received data to the seven segment decoder. Case Supplement In the actual product design or amateur electronic production, the coding chip must be able to complete the required function, then it is necessary to understand how the encoded chip is encoded. Only when we know the encoding method, can we use the microcontroller or digital circuit to customize the decoding scheme.)
Platform: | Size: 924672 | Author: 明德扬科教 | Hits:
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