Search - uart vhdl quartus

[Other resource] uart

Description: VHDL编写的异步通信串行口设计用Quartus工具编译
Platform: | Size: 213116 | Author: 朱兆斌 | Hits:

[VHDL-FPGA-Verilog] VHDL_processor

Description: 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Platform: | Size: 742400 | Author: 赵康 | Hits:

[Windows Develop] edaeda

Description: 完整的串行通信电路vhdl代码，已经通过quartus4.0编译-complete serial communication circuit VHDL code, the compiler has passed quartus4.0
Platform: | Size: 1024 | Author: 鲁东旭 | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[VHDL-FPGA-Verilog] 8051-vhdl-code

Description:
Platform: | Size: 98304 | Author: 周华茂 | Hits:

[Software Engineering] FPGAUART

Description: 用VHDl设计UART的文章，使用QuartusII平台-Design with VHDL UART article, use QuartusII platform
Platform: | Size: 136192 | Author: 胡玉贵 | Hits:

[Other] uart_IP

Description: altera 的uart ip核，可直接调用在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 5120 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] eeprom

Description: eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！-EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Platform: | Size: 521216 | Author: | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Platform: | Size: 212992 | Author: 朱兆斌 | Hits:

[VHDL-FPGA-Verilog] sinwave

Description: 正弦波信号发生的源码，有详细文档说明在quartus上创建工程到仿真、下载的步步操作-Sine wave signal source, has detailed documents created in the Quartus simulation works, download the step-by-step operation
Platform: | Size: 2471936 | Author: benyue | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
Platform: | Size: 212992 | Author: Carlin | Hits:

[Other] EP1C3_12_7_SPCTR

Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to achieve, and deposited LPM_RAM. The design of a UART module (state machine is realized), the data can be sent to the PC machine.
Platform: | Size: 214016 | Author: deadtomb | Hits:

[VHDL-FPGA-Verilog] UART

Description: 實作UART 介面 4 byte 傳送或 4 byte 接收開發環鏡 quartus 且附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
Platform: | Size: 1055744 | Author: 許大頭 | Hits:

[VHDL-FPGA-Verilog] uart_read_send

Description: uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
Platform: | Size: 417792 | Author: binbin | Hits:

[VHDL-FPGA-Verilog] UART

Description: 语言：verilog语言功能：通过串口控制模块，实现FPGA与串口通信。仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
Platform: | Size: 64512 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于VHDL语言的fpga uart 口通讯的源程序，经验证可用，开发环境Quartus -VHDL UART QUARTUS II
Platform: | Size: 4096 | Author: 谢家 | Hits:

[VHDL-FPGA-Verilog] my_uart

Description: 使用VHDL描述的简单的串口通讯，在Quartus上验证过，包含所有文件-this is a simple uart
Platform: | Size: 446464 | Author: 路政西 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart串口通讯，波特率任意可调，采用vhdl语言编写，ise和quartus均可使用-uart serial communication baud rate of any adjustable
Platform: | Size: 3072 | Author: 常飞 | Hits:

[Windows Develop] FEP1C3_12_7_SP

Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。已通过测试。 -FPGA-based signal acquisition and spectrum analysis, using VHDL prepared compression bag Quartus engineering. AD sampling using the state machine to achieve now, and into the LPM_RAM. Design a UART module (which is also the state machine), the data is sent to the PC. Has passed the test.
Platform: | Size: 215040 | Author: l2003l | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-QUARTUS

Description: uart vhdl quartus for altera
Platform: | Size: 212992 | Author: gilang | Hits:

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[Other resource] uart

[VHDL-FPGA-Verilog] VHDL_processor

[Windows Develop] edaeda

[Software Engineering] verilog50%

[VHDL-FPGA-Verilog] 8051-vhdl-code

[Software Engineering] FPGAUART

[Other] uart_IP

[VHDL-FPGA-Verilog] eeprom

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] sinwave

[VHDL-FPGA-Verilog] uart

[Other] EP1C3_12_7_SPCTR

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart_read_send

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] my_uart

[VHDL-FPGA-Verilog] uart

[Windows Develop] FEP1C3_12_7_SP

[VHDL-FPGA-Verilog] UART-VHDL-QUARTUS

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