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[VHDL-FPGA-Verilog] CUS_SPI-VHDL

Description: 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Platform: | Size: 4096 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] SPI_VHDL

Description: SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Platform: | Size: 13312 | Author: efly | Hits:

[Other] spi

Description: VHDL 实现的SPI接口，在Altera EMP7128 上应用过-VHDL SPI interface, the application of Altera EMP off
Platform: | Size: 1024 | Author: 陈同 | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[SCM] SPI

Description: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
Platform: | Size: 72704 | Author: 蓝天 | Hits:

[VHDL-FPGA-Verilog] spi

Description: 用vhdl编写的spi接口程序，在epm7128上仿真成功。-VHDL prepared using spi interface program, in the simulation epm7128 success.
Platform: | Size: 1024 | Author: 邓立新 | Hits:

[Embeded-SCM Develop] sd+spi

Description: sd 的spi模式详细的中文资料，一位好心人翻译的-sd of the spi mode in detail the information the Chinese, a translation of well-wishers
Platform: | Size: 1821696 | Author: 黄天乐 | Hits:

[VHDL-FPGA-Verilog] spi

Description: 一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
Platform: | Size: 18432 | Author: 杨子树 | Hits:

[VHDL-FPGA-Verilog] vspi

Description: spi总线控制器，包含vhdl和verilog两种代码方式来实现。-spi bus controller, including VHDL and Verilog code in two ways to achieve.
Platform: | Size: 13312 | Author: wangdong | Hits:

[VHDL-FPGA-Verilog] SPI_Interface

Description: SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程-SPI interface of the VHDL code can be achieved with SCM spi communication, complete works
Platform: | Size: 4096 | Author: wanyou2345 | Hits:

[VHDL-FPGA-Verilog] SimpleSpi

Description: SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
Platform: | Size: 180224 | Author: dushibiao | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[Embeded-SCM Develop] AIC

Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: | Size: 2048 | Author: 张键 | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:

[VHDL-FPGA-Verilog] SPI

Description: 基于FPGA的SPI控制器的设计，有代码和相关文档资料-the design of SPI controlor ,including verilog codes and other documents
Platform: | Size: 7060480 | Author: yanjinjin | Hits:

[VHDL-FPGA-Verilog] simple_spi

Description: complete spi core written in vhdl. its easy to use and can be configured to operate at various clock frequencies. tested on an ADC to verify the operation
Platform: | Size: 584704 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] spi_dac

Description: driver for spi DAC in VHDL
Platform: | Size: 1024 | Author: Hung | Hits:

[VHDL-FPGA-Verilog] SPI

Description: VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line
Platform: | Size: 585728 | Author: ldong1989 | Hits:

[Other] SPI

Description: 使用VHDL写的SPI Master模块(Using the SPI Master module written in VHDL)
Platform: | Size: 2048 | Author: BY冬子 | Hits:
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