Search - simple uart vhdl

[Other resource] 一个简单的UART

Description: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Platform: | Size: 3654 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 一个简单的UART

Description: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] VHDL_processor

Description: 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Platform: | Size: 742400 | Author: 赵康 | Hits:

[VHDL-FPGA-Verilog] ISE_uart

Description: 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
Platform: | Size: 936960 | Author: sk | Hits:

[VHDL-FPGA-Verilog] uart0vhdl

Description: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Platform: | Size: 1024 | Author: 刘音 | Hits:

[Linux-Unix] UART

Description: 自己用VHDL写的一个串口程序，调试成功，并且用到了项目中，希望初学者可以借鉴下-Their use VHDL to write a serial program, debug the success of the project and used in the hope that beginners can learn from the next
Platform: | Size: 306176 | Author: yanglei | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串行接口UART的用VHDL语言的简单实现，希望对大家有帮助-UART serial interface of the VHDL language with the simple realization, in the hope that everyone has to help
Platform: | Size: 3072 | Author: wangyd | Hits:

[VHDL-FPGA-Verilog] UART1

Description: 自己编写的UART模块用VHDL实现，简单实用-I have written UART modules use VHDL realization of simple and practical
Platform: | Size: 3072 | Author: L | Hits:

[VHDL-FPGA-Verilog] uart_exam

Description: VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
Platform: | Size: 1024 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] miniUart

Description: 一个简单的uart的VHDL描述，希望对大家有点帮助-A simple UART in VHDL description, I hope all of you a little help
Platform: | Size: 19456 | Author: 肖冠兰 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Platform: | Size: 587776 | Author: 李欣 | Hits:

[VHDL-FPGA-Verilog] miniuart.tar

Description: 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL description with a simple UART interface
Platform: | Size: 6144 | Author: elvis | Hits:

[Other] uart_test_ok_921

Description: 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
Platform: | Size: 379904 | Author: wmd | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[Embeded-SCM Develop] UART

Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Platform: | Size: 45056 | Author: sandeep | Hits:

[Com Port] RS232

Description: simple example for uart on fpga
Platform: | Size: 714752 | Author: Jay | Hits:

[VHDL-FPGA-Verilog] UART

Description: This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
Platform: | Size: 1024 | Author: plcpe | Hits:

[VHDL-FPGA-Verilog] uart

Description: 一个简单的UART程序，包括接收，发送，波特率产生-A simple UART program, including receiving, sending, baud rate generation
Platform: | Size: 5120 | Author: 洪琳琅 | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] RS232-Simple

Description: A simple UART example for reference in VHDL.
Platform: | Size: 71680 | Author: Cong | Hits:

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[Other resource] 一个简单的UART

[VHDL-FPGA-Verilog] 一个简单的UART

[VHDL-FPGA-Verilog] VHDL_processor

[VHDL-FPGA-Verilog] ISE_uart

[VHDL-FPGA-Verilog] uart0vhdl

[Linux-Unix] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART1

[VHDL-FPGA-Verilog] uart_exam

[VHDL-FPGA-Verilog] miniUart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] miniuart.tar

[Other] uart_test_ok_921

[VHDL-FPGA-Verilog] uart-vhdl-testbench

[Embeded-SCM Develop] UART

[Com Port] RS232

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] FPGA_UART

[VHDL-FPGA-Verilog] RS232-Simple

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