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[assembly language] shiftreg

Description: verilog实现shiftreg，带测试文件。 文件相當完整，可以下載去測試
Platform: | Size: 114842 | Author: stanly | Hits:

[Other resource] shiftreg

Description: 经过精心设计的移位器的代码，并在FPGA硬件平台实现和验证过的
Platform: | Size: 8372 | Author: hewg | Hits:

[assembly language] shiftreg

Description: verilog实现shiftreg，带测试文件。 文件相當完整，可以下載去測試-Verilog realization shiftreg, with the test document. Document rather complete, and can be downloaded to test the
Platform: | Size: 114688 | Author: stanly | Hits:

[VHDL-FPGA-Verilog] shiftreg

Description: 经过精心设计的移位器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed shifter code, and FPGA hardware platform and tested
Platform: | Size: 8192 | Author: hewg | Hits:

[VHDL-FPGA-Verilog] spitoi2s3

Description: spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
Platform: | Size: 5120 | Author: steny | Hits:

[VHDL-FPGA-Verilog] shiftreg

Description: 本代码实现了移位寄存器功能，初学者可借鉴学习-This code implements the shift register functions, beginners can learn to learn
Platform: | Size: 3072 | Author: tom | Hits:

[VHDL-FPGA-Verilog] shiftreg

Description: Shift regisiter altera de1 board example
Platform: | Size: 1024 | Author: Jhon | Hits:

[VHDL-FPGA-Verilog] shiftreg

Description: Shift register design for vhdl， test passed already!
Platform: | Size: 226304 | Author: tsincons | Hits:

[VHDL-FPGA-Verilog] ShiftReg

Description: 算术移位寄存器和逻辑移位寄存器的简单设计，内附详细説明。-Arithmetic shift register and logic shift register of simple design, containing a detailed description.
Platform: | Size: 445440 | Author: 仲崇鑫 | Hits:

[VHDL-FPGA-Verilog] shiftReg

Description: It s shift register and adder that add 2 bits
Platform: | Size: 104448 | Author: Hadi | Hits:

[VHDL-FPGA-Verilog] the_design_basedonfpga

Description: 1. clkdiv 介绍时钟分频器的建模 2. counter 介绍计数的建模 3. dtrig 介绍D触发器的建模 4. jktrig 介绍JK触发器的建模 5. shiftreg 介绍移位寄存器的建模 6. ttrig 介绍T触发器的建模-The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the modeling of the JK flip-flop 5 introduces the D flip-flop modeling. Shiftreg introduces the modeling of shift register 6 the. ttrig T trigger modeling
Platform: | Size: 576512 | Author: 丁俊辉 | Hits:

[Other] shiftreg

Description: 介绍移位寄存器的VHDL语言建模，适合初学者(Introduce the modeling of shift register)
Platform: | Size: 7907328 | Author: mabang123 | Hits:

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