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[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] xor_mul

Description: 使用列表法，VHDL语言实现的基于多项式基的有限域乘法器，用于AES算法等对有限域乘法有要求的算法-The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested
Platform: | Size: 193536 | Author: zxzx | Hits:

[VHDL-FPGA-Verilog] crc_d8

Description: Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8-Verilog module containing a synthesizable CRC function //* polynomial: (0 1 8) //* data width: 8
Platform: | Size: 1024 | Author: yangyi | Hits:

[Crack Hack] crc

Description: CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset-CRC code generator and calibration program Features: Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
Platform: | Size: 5120 | Author: Alex | Hits:

[Crack Hack] mulf2m

Description: 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。-Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
Platform: | Size: 1024 | Author: 傅建新 | Hits:

[Software Engineering] CRC

Description: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Platform: | Size: 144384 | Author: 黑月 | Hits:

[Crack Hack] freehdl-0.0.6.tar

Description: inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
Platform: | Size: 1391616 | Author: tarik | Hits:

[VHDL-FPGA-Verilog] crc-gen

Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Platform: | Size: 60416 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] rstk.tar

Description: Polynomial solver. This VHDL package synthesizes to a FPGA implementation for a polynomial solver.
Platform: | Size: 184320 | Author: fnts | Hits:

[Algorithm] PID

Description: 簡易的多項視微分積分器 針對四階以下多項式進行運算-polynomial integrator and differentiator
Platform: | Size: 1024 | Author: 風崎 | Hits:

[Software Engineering] ECC

Description: 一种并行的有限域乘法器结构，用于ECC系统构建，多项式基-A parallel Finite Field Multiplier Architecture for ECC system construction, polynomial basis
Platform: | Size: 158720 | Author: 余振华 | Hits:

[Crack Hack] PCK_CRC3_D4

Description: CRC校验码生存程序 校验序列码生成多项式： X16+X13+X12+X11+X10+X8+X6+X5+X2+1 输入数据为16个字节（128位），输出16bit校验序列-CRC, the survival program check sequence code generator polynomial: X16+ X13+ X12+ X11+ X10+ X8+ X6+ X5+ X2+1 input data is 16 bytes (128 bits), output 16bit checksum sequence
Platform: | Size: 1024 | Author: weixin | Hits:

[File Format] vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non- zero initial value optional)
Platform: | Size: 1304576 | Author: 沙爽 | Hits:

[VHDL-FPGA-Verilog] program

Description: Built in self test to such that it generates non redundant inputs to tester using the concept of galois based primitive polynomial.
Platform: | Size: 7168 | Author: Bela | Hits:

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