xor_mul The use of a list of law, VHDL language ba

Title: xor_mul

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
188.88kb
Update:
2008-10-13
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Uploaded by:
profligate

Description: The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested

Downloaders recently: [More information of uploader profligate]

To Search: aes vhdl

[AesCodec] - AES encryption and decryption, in a cate
[GFEMultiplierTaps] - Used to generate GF (2 ^ m) limited doma
[aes_core.tar] - AES realize the Verilog for hardware imp
[rs_encoder] - A very good RS encoder for DVB Channel C
[multiplier] - booth multiplier:
[GFmultiply] - Language Verilog hdl Galois field GF (q)
[aes_crypto_core_latest.tar] - Consecutive AES core Description of proj
[GFverilog-hdl] - Galois field multiplier design, the use

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