Description: An enhanced phase-locked loop (PLL) system is presented
and its properties and performance characteristics
are investigated. Advantages of the proposed PLL
structure over the conventional PLLs including its capability of direct estimation of amplitude and phase angle of its input signal, within a wide range of parameters,are demonstrated. Main features of the proposed PLL are structural simplicity and performance robustness. Performance of the PLL, based on both analog and digital realization, is also presented. Platform: |
Size: 418825 |
Author:yangyansky |
Hits:
Description: ％The phase locked loop(PLL),adjusts the phase of a local oscillator
％w.r.t the incoming modulated signal.In this way,the phase of the
％incoming signal is locked and the signal is demodulated.This scheme
％is used in PM and FM as well.
％We will implement it by using a closed loop system.Control systems
％techniques are applied here.- The phase locked loop (PLL), adjusts the phase of a local oscillator wrt the incoming modulated signal.In this way, the phase of the incoming signal is locked and the signal is demodulated.This scheme is used in PM and FM as well. We will implement it by using a closed loop system.Control systems techniques are applied here. Platform: |
Size: 2048 |
Author:张勇 |
Hits:
Description: 几个锁相环仿真程序－通信技术－不记得哪来的啦。希望有用……。-Several phase-locked loop simulation program- communication technologies- do not remember you come from. Seek to help ... .... Platform: |
Size: 6144 |
Author:纪晓岚 |
Hits:
Description: 一篇简单易懂的关于数字锁相环概念原理设计的经典文章-An easy-to-read digital phase-locked loop on the concept of the classic principles of design article Platform: |
Size: 248832 |
Author:林晓叶 |
Hits:
Description: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking, Platform: |
Size: 1024 |
Author:lily |
Hits:
Description: 基于FPGA设计数字锁相环，提出了一种由微分超前/滞后型检相器构成数字锁相环的Verilog-HDL建模方案-FPGA-based design of digital phase-locked loop, a by the differential ahead of/lag type seizure constitutes a digital phase-locked loop phase of the Verilog-HDL modeling program Platform: |
Size: 504832 |
Author:Zoe |
Hits:
Description: 1、数字锁相环的单片机代码。
2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation. Platform: |
Size: 11264 |
Author:foxmail2008 |
Hits:
Description: 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic Platform: |
Size: 1538048 |
Author:123 |
Hits:
Description: 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation Platform: |
Size: 1024 |
Author:wangxinyi |
Hits:
Description: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
-This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Platform: |
Size: 399360 |
Author:张骅 |
Hits:
Description: 锁相环的MATLAB SIMULINK编程，可以供研究锁相环的人员使用-MATLAB SIMULINK programming the phase-locked loop, you can study for the use of Phase-Locked Loop Platform: |
Size: 10240 |
Author:赵彪 |
Hits:
Description: 完整的锁相环matlab代码实现，其中包括高斯噪声干扰，频差，相差，给出最后频率及相位收敛结果图。重要的是代码中有本人详细注释，易于理解-Complete phase-locked loop matlab code, including the Gaussian noise interference, frequency difference, a difference, given the final results of the frequency and phase diagram convergence. Important that the code in detail in my notes, easy to understand Platform: |
Size: 1024 |
Author:luoshuwen |
Hits:
Description: 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code. Platform: |
Size: 103424 |
Author:采儿 |
Hits:
Search - phase locked loop