Description: FPGA-based design of digital phase-locked loop, a by the differential ahead of/lag type seizure constitutes a digital phase-locked loop phase of the Verilog-HDL modeling program
- [pll] - pll.vhd : PLL written in VHDL hardware l
- [mib-apihook] - MIB apihook injected part of the applica
- [crc] - Prepared using Verilog CRC check codes,
- [dpll_demo] - A simple digital PLL Verilog code, I dra
- [DPLL_verilog] - First-order DPLL VERLOGIC program code,
- [weifenqi] - Differentiator: the use of digital phase
- [DPLL(VHDL)] - The use of VHDL language of digital phas
- [delay_early_gate] - Lead and lag phase-locked loop can be ac
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