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[Communication-Mobile] my_pll

Description: VHDL程序，使用锁相法实现位同步的算法，并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
Platform: | Size: 1759 | Author: 笑容 | Hits:

[SCM] 急救车与交通灯

Description: 急救车与交通灯）（1）南北与东西方向，每个方面由红黄绿三个灯控制（2）南北向：　红（30秒），黄（5秒），绿（25秒）　　　东西向： 红（35秒），黄（5秒），绿（25秒）　　　上述基本参数可以根据实际情况自行调整，灯的变化规律与实际路口规律相同，绿灯在最后5秒钟时，黄灯亮，然后红灯亮，不允许两个方面同时亮绿灯。（3）绿灯的时间显示在数码管上进行显示。（4）可以通过一个开关控制，当开关信号为0时，整个交通灯全灭提高要求：（1）设计一个紧急控制开关信号，当紧急开关信号为1时，两个方向的灯全为红灯。紧急开关撤消后，按照开关按下之前的状态继续运行（其参数要保存）。（2）设计一个夜间行车开关，当开关按下后，两个方向都只有黄灯闪烁，其它灯熄灭。（3）设计两个方向的亮时时间可调。-emergency vehicles and traffic lights) (1) North and South and east-west direction, each with three yellow-green from red lights control (2) to the north and south : red (30 seconds), yellow (5 seconds), Green (25 seconds) to things : red (35 seconds), yellow (5 seconds) Green (25 seconds) above basic parameters can be adjusted to the actual situation, the light changes with the actual law of the same intersection, the green light in the final five seconds, the yellow light is on, and then a red light, bright, not two fronts simultaneously bright green. (3) the green light at the time displayed on the digital display control. (4) can be controlled by a switch, when the switch signal to 0, the whole prospect of traffic lights to improve requirements : (1) Design an emergency control switch
Platform: | Size: 1024 | Author: dd | Hits:

[Communication-Mobile] my_pll

Description: VHDL程序，使用锁相法实现位同步的算法，并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
Platform: | Size: 1024 | Author: 笑容 | Hits:

[source in ebook] subber8

Description: 一个用 VHDL语言编写的冒泡法程序，希望对学习该语言的同学有帮助。-A use of VHDL language bubble law procedures, and they hope to learn the language of the students have to help.
Platform: | Size: 1024 | Author: maomao | Hits:

[matlab] vhdl_fir

Description: 在matlab仿真的基础上，用maxplus2实现等波纹法的程序代码-In matlab simulation, based on the use of such corrugated maxplus2 realize law code
Platform: | Size: 5120 | Author: 王娟芳 | Hits:

[VHDL-FPGA-Verilog] Barker

Description: 实现基于逐码移位法的7位巴克码集中插入式搜索算法。-Shift-by-code-based law 7 Barker Code focus on plug-in search algorithm.
Platform: | Size: 1024 | Author: 黄虎 | Hits:

[VHDL-FPGA-Verilog] xor_mul

Description: 使用列表法，VHDL语言实现的基于多项式基的有限域乘法器，用于AES算法等对有限域乘法有要求的算法-The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested
Platform: | Size: 193536 | Author: zxzx | Hits:

[Multimedia program] line_alaw

Description: 线性PCM到A律pcm的Verilog编码源程序-Linear PCM to the Verilog code pcm A law source
Platform: | Size: 1024 | Author: 李果霖 | Hits:

[VHDL-FPGA-Verilog] alaw

Description: 使用VHDL实现通信脉冲编码调制（PCM）中的a律转换，并实现串并、并串转换。-Use VHDL to achieve communication pulse code modulation (PCM) of a law conversion, and to achieve and string, and string conversion.
Platform: | Size: 5120 | Author: wl | Hits:

[VHDL-FPGA-Verilog] ulaw

Description: 使用VHDL语言，实现通信脉冲编码调制（PCM）的u律压缩。-Using VHDL language, the realization of communication pulse code modulation (PCM) of u law compression.
Platform: | Size: 5120 | Author: wl | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[VHDL-FPGA-Verilog] MedFilter_VHDL

Description: 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
Platform: | Size: 2048 | Author: mike.chen | Hits:

[VHDL-FPGA-Verilog] A-law_enc

Description: A-law Encoder (VHDL)
Platform: | Size: 2048 | Author: Victor | Hits:

[VHDL-FPGA-Verilog] division

Description: 分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
Platform: | Size: 28672 | Author: 旭东 | Hits:

[VHDL-FPGA-Verilog] t1

Description: 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M greater than law.
Platform: | Size: 1024 | Author: tianson | Hits:

[Crack Hack] freehdl-0.0.6.tar

Description: inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
Platform: | Size: 1391616 | Author: tarik | Hits:

[VHDL-FPGA-Verilog] 04301090a-u-law

Description: mod 16 counter using vhdl
Platform: | Size: 5120 | Author: anupam maurya | Hits:

[assembly language] UART_RS232(VHDL)

Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Platform: | Size: 607232 | Author: 饕餮小宇 | Hits:

[Embeded-SCM Develop] kiugaogao

Description: Using weighted model nodes in the network strength and weight are power law distribution, matlab wavelet analysis program, Various kalman filter design.
Platform: | Size: 5120 | Author: sjugm | Hits:

[Embeded-SCM Develop] urjdp

Description: Using weighted model nodes in the network strength and weight are power law distribution, Using matlab written narrowband noise occurs, There are cycle detection, periodic testing.
Platform: | Size: 4096 | Author: faimunqeifen | Hits:
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