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Description: i2c master code for verilog-i2c master code for Verilog
Platform: |
Size: 247808 |
Author: zhang chi |
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Description: LPC915的I2C模块配置为主机时的接口程序,可直接添加到工程里使用-LPC915 I2C module configuration for the host interface can be directly added to the used in the project
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Size: 3072 |
Author: 王辉堂 |
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Description: -- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
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Size: 5120 |
Author: 郑开科 |
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Description: 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
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Size: 2048 |
Author: hxwf801 |
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Description: Avalon I2C master. Ready to use with SOPC.
Platform: |
Size: 23552 |
Author: Davide Merlani |
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Description: WISHBONE revB2 compiant I2C master core
Platform: |
Size: 5120 |
Author: weixing |
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Description: verilog在cpld上实现i2c主从设备通讯功能-Verilog CPLD achieved in i2c master-slave communication equipment
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Size: 718848 |
Author: nedazq |
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Description: Demo for I2C Master and Slave
Platform: |
Size: 324608 |
Author: 水若寒 |
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Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
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Size: 788480 |
Author: lu |
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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
-IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Platform: |
Size: 889856 |
Author: benny |
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Description:
MICROCHIP 實現I2C的 Master 端 (Firmware) 及 Slave 端 (Hardware) 相對應的程式範例
-err
Platform: |
Size: 4096 |
Author: 陳嘉年 |
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Description: 该程序是pic单片机程序,里面含有主从单片机i2c通讯程序。开发环境就是pic单片机的那个专用开发环境。单片机c程序,仅供大家参考。-The program is pic Singlechip procedure, which contains a single-chip i2c master-slave communication procedures. Development environment that is dedicated pic SCM development environment. Singlechip c procedures for your reference.
Platform: |
Size: 211968 |
Author: 刘柱 |
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Description: 基于FPGA的I2C总线主控器的设计与实现-Based on the I2C bus master FPGA Design and Implementation
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Size: 1024 |
Author: wang |
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Description: 用verilog HDL实现I2C Master Controller 的设计,包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
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Size: 211968 |
Author: zbs |
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Description: wishbone i2c master vhdl code
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Size: 5120 |
Author: 磊 |
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Description: i2c IP核
i2c.master
i2c.mater.v-i2c IP core
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Size: 181248 |
Author: zhengzhiqiang |
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Description: i2c master controller, free ip
Platform: |
Size: 11264 |
Author: lai |
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Description: PIC单片机I2C通信主模式,内涵Proteus仿真内容-PIC MCU I2C master mode communications, meaning the content of Proteus simulation
Platform: |
Size: 74752 |
Author: 李婧 |
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Description: 用verilog 实现的 iic 总线编程,包括master,和slave的编程,很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
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Size: 2181120 |
Author: 郭天然 |
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Description: I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NE-I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NEEDED
Platform: |
Size: 9216 |
Author: max |
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