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[OtherHSPICE

Description: 最有用的HSPICE简介,原创课件讲义。HUST专用-most useful HSPICE brief, originality courseware overhead. Where on earth is dedicated
Platform: | Size: 301056 | Author: 李四 | Hits:

[Software EngineeringStar-Hspice.pdf

Description: 内含hspcie的使用文档,avant的,纯英文电子书格式-Hspcie the use of the document contains, avant, and plain English e-books format
Platform: | Size: 7163904 | Author: 宇文扬 | Hits:

[Other Embeded programpipeline_ADC_PLL

Description: 该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较 器.该比较器采用UMC混合/射频0.18肛m 1P6M P衬底双阱CMOS工艺设计,工作电压为 1.8 V.该比较器的灵敏度为0.215 mV,最大失调电压为12 mV,差分输入动态范围为1.8 V,分辨率为8位,在40 M的工作频率下,功耗仅为24.4 ttW.基于0.18 gm工艺的仿真结 果验证了比较器设计的有效性.-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·- verter WBS presented.The comparator WaS d髑igned under UMC Mixed.Mode/RF 0.18 btm 1P6M P.Sub Twin— Well CMOS process and worked with 1.8V power supply.The sensitivity of the comparator was 0.215 mV, the largest offset voltage was 12 mV,the differentiaI input range Was 1.8 V,the resolution was 8 bit and the power dissipation Was only 24.4 gW at 40 MHz.HSPICE simulations of the comparator implemented in a 0.18 um technology demonstrate its effectiveness.
Platform: | Size: 361472 | Author: 赵恒 | Hits:

[Software EngineeringDesign-of-an-Operational-Amplifier

Description: disign whit HSPICE: Design and simulate a two stage CMOS operational amplifier shown in the Fig., for these conditions:  DC Voltage Gain > 60dB  Unity Gain Bandwidth > 70MHz  Phase Margin > 50 degrees  Power Dissipation: as low as possible  Technology: 2μm  Power Supply: 3.3V  Load Capacitance: 2pF  Output Voltage Swing > 2Vp-p  Make a unity feedback buffer and check the settling time of the circuit when you inject a step voltage to the input with rise and fall time of 1μs. Document your results in a written report including design procedure and all of simulations. You also should highlight the most important features of the design.-disign whit HSPICE: Design and simulate a two stage CMOS operational amplifier shown in the Fig., for these conditions:  DC Voltage Gain > 60dB  Unity Gain Bandwidth > 70MHz  Phase Margin > 50 degrees  Power Dissipation: as low as possible  Technology: 2μm  Power Supply: 3.3V  Load Capacitance: 2pF  Output Voltage Swing > 2Vp-p  Make a unity feedback buffer and check the settling time of the circuit when you inject a step voltage to the input with rise and fall time of 1μs. Document your results in a written report including design procedure and all of simulations. You also should highlight the most important features of the design.
Platform: | Size: 47104 | Author: jack | Hits:

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