Description: A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·-
verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin—
Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV，
the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the
power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18
um technology demonstrate its effectiveness．
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