Description: 帧同步模块的Veriolog源码。
在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document. Platform: |
Size: 24576 |
Author:刘仪 |
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Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform Platform: |
Size: 6144 |
Author:liu |
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Description: 本设计采用Cypress公司支持USB2.0协议标准的EZ-USB FX2系列之CY7C68013芯片作为帧同步信号发送器的USB接口芯片，在uVision2开发环境下利用Keil C51完成了满足帧同步信号发送器基本要求的固件设计，具体采用了批量传输方式、大端点三缓冲设置、定时器中断方式的同步脉冲和数据的发送、软FIFO方式数据存放以及I2C总线下的LED显示等技术，最后协助编写USB底层驱动程序实现了固件自动下载。经过测试，所设计的帧同步信号发送器基本达到了课题所要求的基本原理性设计与验证。
-This design uses Cypress supports USB2.0 protocol standards of EZ-USB FX2 Series CY7C68013 chip as a frame synchronization signal transmitter of the USB interface chip, in uVision2 development environment using Keil C51 completed a frame synchronization signal to meet the basic requirements of transmitter firmware design, specific use of a bulk transfer mode, the endpoint buffer three settings, the timer interrupt the sync pulse and data transmission, soft FIFO mode and the I2C bus data repository under the LED display technology, assist in the preparation of the final bottom USB driver to achieve the firmware is automatically downloaded. After testing, the design of frame synchronization signal transmitter basic subjects required to achieve the basic principles of design and verification. Platform: |
Size: 603136 |
Author:xmuyfng |
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Description: 详细讲解了同步原理，包括载波同步、位同步、帧同步-Detailed account of the principle of synchronization, including the carrier synchronization, bit synchronization, frame synchronization Platform: |
Size: 307200 |
Author:wuqianye |
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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz Platform: |
Size: 2048 |
Author:张键 |
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Description: 基于Verilog语言的数字通信系统的帧同步的实现原理以及Verilog代码实现-Verilog language-based digital communications system, the realization of the principle of frame synchronization as well as the Verilog code Platform: |
Size: 481280 |
Author:黄虎 |
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Description: in his name
this code is simulation of cox algorithm for ofdm synchronization in WIMAX down link systems.
it send 2 frame via awgn channel and uses from correlation to detect the beginning of frame.
.-in his name
this code is simulation of cox algorithm for ofdm synchronization in WIMAX down link systems.
it send 2 frame via awgn channel and uses from correlation to detect the beginning of frame.
. Platform: |
Size: 1024 |
Author:amin |
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Description: 一个完整的巴克吗帧同步检测程序。并且包含同步保护，同步判断检测等功能，可直接运用。程序包含注释和仿真说明，验证通过具有不错的效果。-Buck do a complete frame synchronization detection program. And includes synchronization protection, synchronization to determine detection and other functions, can be directly used. Simulation process consists of notes and instructions, validate through with good results. Platform: |
Size: 1595392 |
Author:Kerwin |
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Description: 各种同步实验及系统设计。包括：同步载波提取、帧同步信号提取实验、位同步信号提取实验以及衰落信道帧同步电路设计与实现和位同步的提取方法设计。-Various synchronization experiment and system design. Including: synchronous carrier extraction, frame synchronization signal extraction experiments, bit synchronization signal extraction experiment and fading channel frame synchronization circuit design and implementation and bit synchronization method of extracting the design. Platform: |
Size: 355328 |
Author:Kerwin |
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Description: ofdm系统中的完整帧同步模块，基于verilog实现。-ofdm system full frame synchronization module, based on verilog implementation. Platform: |
Size: 571392 |
Author:罗云 |
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Description: 分析帧同步算法，提供帧同步的状态机实现图以及得到的正确仿真图形。-Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics. Platform: |
Size: 96256 |
Author:李逊 |
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Description: 基于能量差分的ofdm帧同步算法matlab程序，可以运行-OFDM frame synchronization based on energy difference of the received preamble，can run Platform: |
Size: 1024 |
Author:邢昊 |
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Description: OFDM系统中的帧同步算法和理论分析，很好的学习材料-Frame synchronization in OFDM system algorithms and theoretical analysis, a very good learning materials Platform: |
Size: 481280 |
Author:fy |
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Description: 帧同步状态机主要是为了克服通信中可能出现的各种意外情况，包括信号丢失、信道误码等造成的通信中断，尽量维护正常的通信的进行。当系统启动后，同步状态机处于失步态，并且不断搜索输入信号中的有效同步模式（“10011011”），一旦当其找到一个有效的同步模式后，进入预同步态；在预同步态还不能完全确定当前找到的帧开始位置（由同步模式确定的位置）是正确的，还需要继续检查2个相隔一个帧长（256个时钟）后的位置是否仍然存在有效的同步模式，如果存在那么同步状态机将进入同步态，否则将返回失步态继续搜索下一个有效的同步模式；在同步态时，状态机不断检测每一帧的帧头位置是否存在有效的同步模式，如果一帧的开始位置没有检测到同步模式，那么将进入保持态，此时还不能确定接收信号的帧头位置已经丢失，还需要根据相邻下3帧的情况进行判定，如果相邻下3帧的帧头位置仍然没有检测到有效的同步模式，那么认为帧结构已经丢失，进入失步态重新进行搜索，如果在某一帧的帧头位置检测到了有效的同步模式，那么认为帧结构没有丢失（上一帧的无效同步模式是由于误码所致），返回同步态。-Frame synchronization state machine is mainly to overcome all kinds of unexpected situations that may occur in communications, including loss of signal, the communication channel error caused by the interruption, try to maintain a normal communicate. When the system starts, synchronous state machine is out of gait, and continues to search for a valid input signal synchronous mode (" 10011011" ), as soon as it finds a valid synchronous mode, enter the pre-synchronization state in pre-synchronization state also can not completely determine the start position of the current frame is found (as determined by the synchronization mode position) are correct, but also the need to continue to check whether the two separated one frame length (256 clocks) after the location is still valid in the synchronous mode, if present, then synchronous state machine will enter the synchronized state, otherwise it will return loss gait continue to search for the next valid synchronization pattern in Platform: |
Size: 4096 |
Author:刘旭 |
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Search - frame synchronization