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[Other resource] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key -- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424510 | Author: 呈一 | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[VHDL-FPGA-Verilog] FusionStarterKit_Board_DesignFiles

Description: 这是ACTEL的FPGA完整开发文挡 含测试源码！（不可分割）-This is a complete FPGA development ACTEL the text block containing the test-source! (Integral)
Platform: | Size: 5435392 | Author: nanotalk | Hits:

[VHDL-FPGA-Verilog] CIC

Description: 介绍了积分梳状滤波器(CIC)设计，压缩包里面有程序的流程图，采用verilogHDL编写，在modelsim上可以实现仿真结果，非常不错-Introduced the integral comb filter (CIC) design, there are procedures for compressed packets flow chart, using verilogHDL prepared on the ModelSim simulation results can be achieved very good
Platform: | Size: 153600 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] CIC

Description: cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design
Platform: | Size: 1024 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilog] BPSK_track_10.23M_BD_IF46.52MHz

Description: in tracking programm，actualize communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result-communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result
Platform: | Size: 3322880 | Author: laonong | Hits:

[VHDL-FPGA-Verilog] VHDL_fre_div

Description: 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider Design, including even frequency, duty cycle and 50 of non-50 duty cycle of the odd frequency, half-integer (N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of With the circuit, and on the ModelSim verification.
Platform: | Size: 322560 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] 232543

Description: FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers
Platform: | Size: 823296 | Author: Revathy | Hits:

[VHDL-FPGA-Verilog] FPGA-PID-

Description: FPGA闭环控制电路积分分离式PID算法子程序 算法函数 中断函数-Integral closed loop control circuit FPGA PID algorithm separate interrupt function subroutine algorithm function
Platform: | Size: 73728 | Author: 一 | Hits:

[VHDL-FPGA-Verilog] FPGA-based--DC-speed-controller

Description: 针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器-Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller
Platform: | Size: 113664 | Author: 史夏波 | Hits:

[VHDL-FPGA-Verilog] cic_hb

Description: 用FPGA设计的cic和hb滤波器（积分疏状滤波器核半带滤波器）初学FPGA 的同学可以看一下啊-Using the FPGA design cic and hb filter (integral scanty shape filter nuclear half took filter)
Platform: | Size: 13296640 | Author: junjun | Hits:

[Crack Hack] aes-encryption

Description: 为实现AES加密设计的高速实现，本设计引进了一种AES的并行设计算法，整体结构和加密进程，基于FPGA本身的特征和算法，设计使用并行处理算法来实现并行处理进程。-To implement the design of the AES algorithm with a high speed, the thesis introduce the principia mathematica of AES algorithm, integral structure and the Encryption process. Based on the algorithm and the characteristics of FPGA, the design uses the pipelining method and realizes the parallel processing.
Platform: | Size: 6144 | Author: 许飞 | Hits:

[VHDL-FPGA-Verilog] VHDL-divider-design

Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
Platform: | Size: 320512 | Author: 黄玲 | Hits:

[VHDL-FPGA-Verilog] Prescaler-to-use-VHDL-design

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and integral crossover frequency. All can be achieved through Synplify Pro FPGA synthesizer manufacturer or integrated to form a circuit that can be used and verified in ModelSim.
Platform: | Size: 339968 | Author: liufei | Hits:

[VHDL-FPGA-Verilog] MultCIC

Description: 三级梳状积分CIC滤波器的FPGA实现代码，包括积分模块，抽取模块和梳状模块以及顶层模块的实现代码-Three integral CIC comb filter FPGA implementation code, including the integration module, extraction module and a comb and a top-level module module implementation code
Platform: | Size: 3476480 | Author: xuweiwei | Hits:

[LabView] cic3_decimator

Description: 积分梳状滤波器(CIC)设计在FPGA上的应用-Application of integral comb filter (CIC) for FPGA
Platform: | Size: 1024 | Author: 高浚玮 | Hits:

[Embeded-SCM Develop] yingpang

Description: Minimum mean square error MSE calculation algorithm, It contains positional PID algorithm, integral separate PID, Thermonuclear using weighting factor.
Platform: | Size: 4096 | Author: fengiemangmiu | Hits:

[VHDL-FPGA-Verilog] ethernet_loopback

Description: 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
Platform: | Size: 23942144 | Author: marktuwen | Hits:

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