Search - file vhdl

[WEB Code] vhdl

Description: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools.
Platform: | Size: 173517 | Author: gbj | Hits:

[VHDL-FPGA-Verilog] i2c总线的vhdl实现和vxworks的文件系统

Description: i2c总线的vhdl实现和vxworks的文件系统-i2c bus VHDL realization and VxWorks file system
Platform: | Size: 16384 | Author: | Hits:

[USB develop] cy7c68013

Description: usb 2.0 cy7c68013 pdf file
Platform: | Size: 516096 | Author: flight_bai | Hits:

[VHDL-FPGA-Verilog] FFT_VHDL

Description: FFT的VHDL源文件，经过在Quartus II上的测试无错误-FFT of the VHDL source file, after the Quartus II on the test error
Platform: | Size: 28672 | Author: 沈克镇 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools. -This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampterms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using anysynthesised using current synthesis tools.
Platform: | Size: 173056 | Author: gbj | Hits:

[MacOS develop] REG32

Description: 32位寄存器的VHDL的原代码下载,COOLCOOLCOOL-32-bit register of the original VHDL code download, COOLCOOLCOOL
Platform: | Size: 3072 | Author: LIU | Hits:

[VHDL-FPGA-Verilog] pcfg

Description: ISE file VHDL code about the comunication from PC to kit in process writing and reading from BRAM in kit
Platform: | Size: 7273472 | Author: Rakhun | Hits:

[matlab] CDMACoax

Description: this a mix file.in this cdma vhdl ,simulink file included-this is a mix file.in this cdma vhdl ,simulink file included
Platform: | Size: 54272 | Author: amisha | Hits:

[VHDL-FPGA-Verilog] file_io

Description: 读写硬盘文件的VHDL仿真例程，该例程能够帮助FPGA设计人员读取硬盘的数据文件输入仿真环境，并且将仿真后的数据存入硬盘-test bench for reading and writing disk files
Platform: | Size: 1024 | Author: season Li | Hits:

[VHDL-FPGA-Verilog] fir1

Description: this file consists of simple FIR filter designed with the fixed coefficients
Platform: | Size: 1024 | Author: bharat kumar | Hits:

[VHDL-FPGA-Verilog] finalcoursework

Description: 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
Platform: | Size: 43008 | Author: 三木 | Hits:

[Windows Develop] 001.File.Joiner.and.Splitter.v4.0.5.0-RedT_nled.z

Description: test of vhdl 74 code
Platform: | Size: 3492864 | Author: kang | Hits:

[VHDL-FPGA-Verilog] DWT-VHDL

Description: 小波变换的VHDL代码，内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.
Platform: | Size: 18432 | Author: Janee | Hits:

[VHDL-FPGA-Verilog] test

Description: 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to
Platform: | Size: 1024 | Author: 陈乾 | Hits:

[VHDL-FPGA-Verilog] code

Description: register file using verilog
Platform: | Size: 4096 | Author: tran | Hits:

[VHDL-FPGA-Verilog] RC6-block-cipher-using-VHDL

Description: VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped
Platform: | Size: 55296 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] HASH-code-implementation-using-VHDL

Description: implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.
Platform: | Size: 14336 | Author: waleed | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: this file contains vhdl code for aes
Platform: | Size: 119808 | Author: baby | Hits:

[VHDL-FPGA-Verilog] 按键去抖电路VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 29696 | Author: lixilin | Hits:

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