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[VHDL-FPGA-Verilog] ETHERNET

Description: 具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述-With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description
Platform: | Size: 69632 | Author: winwalk | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode.tar

Description:
Platform: | Size: 740352 | Author: hrui | Hits:

[VHDL-FPGA-Verilog] Tri-mode_Ethernet_MAC_Specifications

Description: document for mac 10 100 1000 ethernet verilog code.you find code in this site
Platform: | Size: 247808 | Author: amir | Hits:

[VHDL-FPGA-Verilog] 10100MIP

Description: 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
Platform: | Size: 740352 | Author: 打狗队 | Hits:

[Other] FPGA-DM9000A

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A for Verilog realization of Ethernet data sent and received
Platform: | Size: 2658304 | Author: qmy | Hits:

[source in ebook] verilog

Description: verilog描述的以太网MAC层源代码，功能正确，已经在FPGA开发板上测试！需要的赶紧下-verilog description of the Ethernet MAC layer source code, function correctly, has been tested in the FPGA development board! Need to hurry the next! ! !
Platform: | Size: 56320 | Author: WangYong | Hits:

[VHDL-FPGA-Verilog] ethernet_controller_Verilog

Description: 以太网控制器源码，verilog语言,包含MAC、MII接口-Ethernet controller ,include MAC and MII interfaces ,by verilog
Platform: | Size: 71680 | Author: CL | Hits:

[VHDL-FPGA-Verilog] MACtop

Description: 基于FPGA的以太网控制器（MAC）源码，包括发送、接收、控制、CRC、寄存器、计数器等模块-Ethernet MAC sub-layer protocol
Platform: | Size: 128000 | Author: cmf | Hits:

[VHDL-FPGA-Verilog] MII

Description: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Platform: | Size: 2048 | Author: 雷伟林 | Hits:

[VHDL-FPGA-Verilog] EtherNet

Description: 以太网控制器的FPGA实现,用Verilog语言编写!-Ethernet controller FPGA, Verilog language!
Platform: | Size: 142336 | Author: Shawn | Hits:

[VHDL-FPGA-Verilog] EMAC6

Description: verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.
Platform: | Size: 3602432 | Author: trygov | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
Platform: | Size: 788480 | Author: AricSnow | Hits:

[VHDL-FPGA-Verilog] FPGADM9000AVerilog

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
Platform: | Size: 4200448 | Author: `ians | Hits:

[VHDL-FPGA-Verilog] FPGADM9000AVerilog

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
Platform: | Size: 2800640 | Author: 飞翔 | Hits:

[VHDL-FPGA-Verilog] PHY_MDIO

Description: 光纤模块实现点对点通信，千兆网传输，基于FPGA，采用Verilog语言进行编程，实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
Platform: | Size: 1111040 | Author: Grace | Hits:

[VHDL-FPGA-Verilog] eth

Description: 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
Platform: | Size: 24576 | Author: 小刚 | Hits:

[VHDL-FPGA-Verilog] udp_send1

Description: 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Platform: | Size: 53248 | Author: qiubin | Hits:

[VHDL-FPGA-Verilog] 14_ethernet_test

Description: 这是利用FPGA实现对以太网传输的控制。FPGA为Spartan 6 LX16，以太网芯片为RTL8211。千兆传输速率。语言为Verilog，但没找到这一选项，故选择了最接近的VHDL-This is achieved using the FPGA Ethernet transmission control. FPGA for the Spartan 6 LX16, Ethernet chip RTL8211. Gigabit transmission rate.
Platform: | Size: 7380992 | Author: accountm | Hits:

[VHDL-FPGA-Verilog] eth_Management_interface

Description: 千兆网的FPGA代码，非常有用的，请大家阅读(ethernet verilog coding,please read it and download it)
Platform: | Size: 5120 | Author: TONYSSSS | Hits:

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