ethernet_controller_Verilog Ethernet controller ,i

Title: ethernet_controller_Verilog

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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
70kb
Update:
2012-11-26
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Uploaded by:
bingyuxxlove

Description: Ethernet controller ,include MAC and MII interfaces ,by verilog

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To Search: Verilog MII Verilog ethernet

[SPI_Code(Verilog)] - SPI bus under the Verilog hardware descr
[mii] - MII Ethernet PHY port physical layer tra
[PIC18F97J60] - PIC18F97J60 series of single-chip Ethern
[Timer] - msp430 learning materials, including sch
[ethernet_tri_mode.tar] - Ethernet-based incentive program write v
[MII] - This is simple, but very comprehensive n
[ML403] - XILINX Virtex-4 in the example of Ethern
[ETH] - The system top-level module, called the

File list (Check if you may need any files):

Filename Size Date
以太网控制器Verilog源码(含有MAC MII接口)\rtl\verilog\Clk_ctrl.v
........................................\...\.......\eth_miim.v
........................................\...\.......\header.v
........................................\...\.......\MAC_rx\Broadcast_filter.v
........................................\...\.......\......\CRC_chk.v
........................................\...\.......\......\MAC_rx_add_chk.v
........................................\...\.......\......\MAC_rx_ctrl.v
........................................\...\.......\......\MAC_rx_FF.v
........................................\...\.......\MAC_rx
........................................\...\.......\MAC_rx.v
........................................\...\.......\MAC_top.v
........................................\...\.......\.....x\CRC_gen.v
........................................\...\.......\......\flow_ctrl.v
........................................\...\.......\......\MAC_tx_addr_add.v
........................................\...\.......\......\MAC_tx_Ctrl.v
........................................\...\.......\......\MAC_tx_FF.v
........................................\...\.......\......\Ramdon_gen.v
........................................\...\.......\MAC_tx
........................................\...\.......\MAC_tx.v
........................................\...\.......\miim\eth_clockgen.v
........................................\...\.......\....\eth_outputcontrol.v
........................................\...\.......\....\eth_shiftreg.v
........................................\...\.......\....\timescale.v
........................................\...\.......\miim
........................................\...\.......\Phy_int.v
........................................\...\.......\reg_int.v
........................................\...\.......\RMON\RMON_addr_gen.v
........................................\...\.......\....\RMON_ctrl.v
........................................\...\.......\....\RMON_dpram.v
........................................\...\.......\RMON
........................................\...\.......\RMON.v
........................................\...\.......\TECH\altera\CLK_DIV2.v
........................................\...\.......\....\......\CLK_SWITCH.v
........................................\...\.......\....\......\duram.v
........................................\...\.......\....\altera
........................................\...\.......\....\CLK_DIV2.v
........................................\...\.......\....\CLK_SWITCH.v
........................................\...\.......\....\duram.v
........................................\...\.......\....\xilinx\CLK_DIV2.v
........................................\...\.......\....\......\CLK_SWITCH.v
........................................\...\.......\....\......\duram.v
........................................\...\.......\....\xilinx
........................................\...\.......\TECH
........................................\...\verilog
........................................\rtl
以太网控制器Verilog源码(含有MAC MII接口)

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Filename	Size	Date
以太网控制器Verilog源码(含有MAC	MII接口)\rtl\verilog\Clk_ctrl.v
........................................\...\.......\eth_miim.v
........................................\...\.......\header.v
........................................\...\.......\MAC_rx\Broadcast_filter.v
........................................\...\.......\......\CRC_chk.v
........................................\...\.......\......\MAC_rx_add_chk.v
........................................\...\.......\......\MAC_rx_ctrl.v
........................................\...\.......\......\MAC_rx_FF.v
........................................\...\.......\MAC_rx
........................................\...\.......\MAC_rx.v
........................................\...\.......\MAC_top.v
........................................\...\.......\.....x\CRC_gen.v
........................................\...\.......\......\flow_ctrl.v
........................................\...\.......\......\MAC_tx_addr_add.v
........................................\...\.......\......\MAC_tx_Ctrl.v
........................................\...\.......\......\MAC_tx_FF.v
........................................\...\.......\......\Ramdon_gen.v
........................................\...\.......\MAC_tx
........................................\...\.......\MAC_tx.v
........................................\...\.......\miim\eth_clockgen.v
........................................\...\.......\....\eth_outputcontrol.v
........................................\...\.......\....\eth_shiftreg.v
........................................\...\.......\....\timescale.v
........................................\...\.......\miim
........................................\...\.......\Phy_int.v
........................................\...\.......\reg_int.v
........................................\...\.......\RMON\RMON_addr_gen.v
........................................\...\.......\....\RMON_ctrl.v
........................................\...\.......\....\RMON_dpram.v
........................................\...\.......\RMON
........................................\...\.......\RMON.v
........................................\...\.......\TECH\altera\CLK_DIV2.v
........................................\...\.......\....\......\CLK_SWITCH.v
........................................\...\.......\....\......\duram.v
........................................\...\.......\....\altera
........................................\...\.......\....\CLK_DIV2.v
........................................\...\.......\....\CLK_SWITCH.v
........................................\...\.......\....\duram.v
........................................\...\.......\....\xilinx\CLK_DIV2.v
........................................\...\.......\....\......\CLK_SWITCH.v
........................................\...\.......\....\......\duram.v
........................................\...\.......\....\xilinx
........................................\...\.......\TECH
........................................\...\verilog
........................................\rtl
以太网控制器Verilog源码(含有MAC	MII接口)