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Description: 有VHDL写的一个38译码器,并付仿真波形.-VHDL has written a decoder 38, and pay the simulation waveform.
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Size: 57344 |
Author: 陈阿水 |
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Description: 加减计数器
library ieee
use ieee. std_logic-_1164.all
entity dec3_8 is
port(a,b,c,s1,s2,s3: in std_logic
y: out std_logic_vector(0 to 7))
end
architecture b of dec3_8 is
signal abc: std_logic_vector(0 to 2)
begin
abc<=a&b&c
process(abc,s1,s2,s3)
Platform: |
Size: 1024 |
Author: 镜辰 |
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