Search - VHDL HD

[File Operate] taix

Description: 8.22出租车计价器VHDL程序与仿真。 --文件名：taxi.hd。 --功能：出租车计价器。 --最后修改日期：2004.4.9。
Platform: | Size: 17617 | Author: 我就没 | Hits:

[Editor] xapp514_hd-integ-demobrd

Description: SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写-SDI interface of the source, including interference coding and string conversion, using VHDL hardware description language
Platform: | Size: 381952 | Author: | Hits:

[File Format] taix

Description: 8.22出租车计价器VHDL程序与仿真。 --文件名：taxi.hd。 --功能：出租车计价器。 --最后修改日期：2004.4.9。 -8.22 Taximeter procedures and simulation of VHDL.- File Name: taxi.hd.- Function: Taximeter.- Last modified date: 2004.4.9.
Platform: | Size: 17408 | Author: 我就没 | Hits:

[VHDL-FPGA-Verilog] WritingTestbenches

Description: 编写testbench的超好教程，网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf-Testbench prepared super good tutorials, on-line this information is relatively small. (Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf
Platform: | Size: 4112384 | Author: 文成 | Hits:

[Audio program] audiofiles

Description: This project provide play audio and record function
Platform: | Size: 12288 | Author: You | Hits:

[DSP program] davincihd_revf_ver6

Description: DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码，是Spectrum Digital, Inc刚开发出来的！ CPLD Firmware Project CPLD Firmware Project (Version 6).-DaVinci HD CPLD Firmware Resources This is the original TI development board DM6467 Schematic of the VHDL code of CPLD is Spectrum Digital, Inc has just developed! CPLD Firmware ProjectCPLD Firmware Project (Version 6).
Platform: | Size: 460800 | Author: liliang | Hits:

[Other] HD

Description: 高清(HD) 达芬奇流媒体应用.rar-High-definition (HD) streaming media applications Vinci. Rar
Platform: | Size: 391168 | Author: Jimmysun | Hits:

[VHDL-FPGA-Verilog] sd_hd_sdi_demo

Description: lattice的SDI DEMO板工程源代码，HD/SD自适应，内有彩条自产生源-designed for lattice sdi
Platform: | Size: 795648 | Author: lqj | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Platform: | Size: 10240 | Author: wei | Hits:

[Com Port] HDLC_VHDL

Description: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Platform: | Size: 11264 | Author: 卓福洲 | Hits:

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[File Operate] taix

[Editor] xapp514_hd-integ-demobrd

[File Format] taix

[VHDL-FPGA-Verilog] WritingTestbenches

[Audio program] audiofiles

[DSP program] davincihd_revf_ver6

[Other] HD

[VHDL-FPGA-Verilog] sd_hd_sdi_demo

[VHDL-FPGA-Verilog] hdlc

[Com Port] HDLC_VHDL

[VHDL-FPGA-Verilog] taxivhdl

[VHDL-FPGA-Verilog] HDLC

[VHDL-FPGA-Verilog] VHDL

[Other] VHDLPractical-tutorial---hd

[VHDL-FPGA-Verilog] HD_top_null

[VHDL-FPGA-Verilog] VHDL-Programming.Hill

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