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[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过
Platform: | Size: 1388 | Author: yangyanwen | Hits:

[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[Software Engineering] ModelSim_SE_6.5_downloads_install_Configuration.ra

Description: 详细的介绍了modelsim的下载，破解，编译xilinx库，配置的问题，非常详细-Described in detail modelsim download, crack, the compiler library xilinx, configuration problems, in great detail
Platform: | Size: 1389568 | Author: wushaojie | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] div_n_0_5

Description: 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
Platform: | Size: 788480 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] modelsim-timing-analysis

Description: 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se6.2b
Platform: | Size: 705536 | Author: 雍振强 | Hits:

[VHDL-FPGA-Verilog] test_pll

Description: 使用modelsim se6.5d仿真altpll锁相环 完整工程，verilog代码，因为没找到选的是vhdl-simulation pll with modelsim se6.5d
Platform: | Size: 2276352 | Author: 杨毅 | Hits:

[VHDL-FPGA-Verilog] fir_lowpass

Description: 硬件语言实现数字低通滤波器，使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
Platform: | Size: 545792 | Author: linzi | Hits:

[ARM-PowerPC-ColdFire-MIPS] SCMIPS

Description: 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Platform: | Size: 134144 | Author: 赵成龙 | Hits:

[Graph program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: shi17395 | Hits:

[VHDL-FPGA-Verilog] handshack

Description: 握手机制的仿真，用ISE14.7打开，modelsim se6.5(Hold the simulation of mobile phone system, open with ISE14.7, Modelsim se6.5.)
Platform: | Size: 70656 | Author: 阿士大夫 | Hits:

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