Search - DDS ISE

[Other resource] dds正弦发生器代码

Description: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Platform: | Size: 491278 | Author: czy | Hits:

[VHDL-FPGA-Verilog] dds正弦发生器代码

Description: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Platform: | Size: 491520 | Author: czy | Hits:

[Documents] dds_test

Description: 此程序在于，调用ISE中自带的DDS__IP，来产生单正弦信号，该程序已通过布线后仿真实现-The program focus on that it utilize the DDS core embedded in the ISE to generate the sigle sinusoid signal and this program have acess to the posted simulation!
Platform: | Size: 1796096 | Author: 艾巍 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] CORDIC_SINE

Description: xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
Platform: | Size: 14447616 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[Other] MD_DDS_10bit_VHDL

Description: 十位DA输出的DDS，用VHDL实现，环境：ISE 8.1，仿真软件：ModelSim_SE_6.1b-10 DA output of the DDS, with the VHDL implementation, environment: ISE 8.1, simulation software: ModelSim_SE_6.1b
Platform: | Size: 1020928 | Author: 爬树跑 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds产生文件源程序，很好用,调用IP核，在ISE中可以使用-dds files generated source code, useful, called IP cores, can be used in the ISE
Platform: | Size: 2048 | Author: wz | Hits:

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

Description: 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
Platform: | Size: 1383424 | Author: francis davis | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[Other Embeded program] sin

Description: 在ISE中用DDS核产生sin函数可用于信号源的产生、信号的调制-generating sin function using IP CORE DDS in ISE
Platform: | Size: 1024 | Author: hongcan | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在ISE环境中，运用verilog语言实现DDS（直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写）的功能-In the ISE environment, use verilog language DDS (direct digital frequency synthesizer (Direct Digital Synthesizer) in abbreviation) of the function
Platform: | Size: 371712 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] dual_ram

Description: 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
Platform: | Size: 2048 | Author: 唐宏伟 | Hits:

[Other] test3

Description: DDS 100MHZ to 4MHZ este DDS esta reado con ISE NAvigator en lenguage VHDL, funciona pero hay diferencias con la cantidad de muestras para crear la onda senoidal, se recomienda aunmentar el numero de muestras para lograr una mejor exactitud de la onda de 4MHZ
Platform: | Size: 834560 | Author: luisazul636 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
Platform: | Size: 5760000 | Author: dfdqzp | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法，调用xilinx IP ，ise(DDS algorithm, call Xilinx IP, ISE)
Platform: | Size: 5728256 | Author: 阿士大夫 | Hits:

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[Other resource] dds正弦发生器代码

[VHDL-FPGA-Verilog] dds正弦发生器代码

[Documents] dds_test

[VHDL-FPGA-Verilog] dds_easy

[VHDL-FPGA-Verilog] CORDIC_SINE

[VHDL-FPGA-Verilog] MyDDS

[Other] MD_DDS_10bit_VHDL

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] ISE_lab17

[Other Embeded program] sin

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dual_ram

[Other] test3

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

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