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[VHDL-FPGA-Verilog] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连-In the Xilinx ISE environment, configure a DCM components, can view the program is running time. Through the serial port and terminal equipment connected to
Platform: | Size: 710656 | Author: 张杰 | Hits:

[Special Effects] DCM

Description: 图像格式转化器！！！！！！！！！！！可以转化dicom格式文件-Image format converter! ! ! ! ! ! ! ! ! ! ! Can be transformed into DICOM format
Platform: | Size: 275456 | Author: Dragonxuep4 | Hits:

[File Operate] DICOMConvert

Description: 提供一个比较好的代码方法,从.dcm到.bmp格式的转换!希望大家满意!-Code to provide a relatively good method. Dcm to. Bmp format conversion! Hope that we satisfied!
Platform: | Size: 5123072 | Author: uil | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[VHDL-FPGA-Verilog] dcm2

Description: 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
Platform: | Size: 1024 | Author: 云 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_FB_SUBM

Description: xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK0_FB_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK0_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLKDV_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[Special Effects] ismsde2000

Description: 这是一个把bmp 图像转换成dcm图像的专用程序-This is a bmp to dcm program
Platform: | Size: 61440 | Author: 曾千里 | Hits:

[VHDL-FPGA-Verilog] xapp462_vhdl

Description: a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
Platform: | Size: 14336 | Author: caoerlin | Hits:

[2D Graphic] dcm

Description: 该代码可以将dicom图像转为bmp图像，非常方便实用，代码简介明了，易于上手-The code can be dicom image to bmp image, very convenient and practical, brief and clear code, easy to fly
Platform: | Size: 4290560 | Author: 王朝阳 | Hits:

[Documents] DCM

Description: Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for the use of VHDL-based cases. This document for personal study and summary
Platform: | Size: 163840 | Author: 张潘睿 | Hits:

[matlab] plantmodel

Description: MOdel to control dcM
Platform: | Size: 5120 | Author: venkat | Hits:

[VHDL-FPGA-Verilog] wtut_sc

Description: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Platform: | Size: 106496 | Author: shad | Hits:

[Windows Develop] Dcm2bmp-bmp2dcm

Description: dcm to bmp and bmp to dcm-It is the code that dcm to bmp and bmp to dcm.
Platform: | Size: 95232 | Author: yanghui | Hits:

[Windows Develop] iii

Description: DCM图像像素分析DCM图像像素DCM图像像素分析分析-DCM image pixel analysis of DCM-pixel image analysis of the image pixel analysis of DCM
Platform: | Size: 230400 | Author: 千纸鹤 | Hits:

[Communication] DICOM3

Description: 1.修改DICOM传输底层服务名。 2.删除FindSCUIsRun属性。 3.删除MoveSCUIsRun属性。 4.删除StopMoveSCU属性。 5.删除StopFindSCU属性。 6.删除OnMoveSCUReceiveFile(sReceivedFileName: String)事件。 7.增加是否将StoreSCP接收文件保存到子目录功能。（StoreSCPSaveFileInSubDir[True=保存到子目录(.\ Modality \ StudyDate \ PatientID \ SOPInstanceUID .dcm),False=保存到接收目录]）-1. Modify the underlying DICOM transmission service name. 2. Remove FindSCUIsRun property. 3. Remove MoveSCUIsRun property. 4. Remove StopMoveSCU property. 5. Remove StopFindSCU property. 6. Delete OnMoveSCUReceiveFile (sReceivedFileName: String) event. 7. StoreSCP whether the increase in the received file to a subdirectory function. (StoreSCPSaveFileInSubDir [True = saved to a subdirectory (. \ Modality \ StudyDate \ PatientID \ SOPInstanceUID . Dcm), False = Save to receive directory])
Platform: | Size: 2119680 | Author: 萧十一 | Hits:

[Other] NS-Flyback-DCM

Description: MathCAD file for the design of Discontinuous Conduction Mode (DCM) Flyback Converter
Platform: | Size: 565248 | Author: Yu Hu Ming | Hits:
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