Search - 74LS138 VH

[Other] 74LS138

Description: 用VHDL 语言描述度三线八线译码器，其开发均在FPGA中-using VHDL description line 8 3 degrees decoder lines, the development is in FPGA
Platform: | Size: 111616 | Author: 侯同 | Hits:

[VHDL-FPGA-Verilog] 74hc138

Description: 74ls138 基于verilog语言的实现 -Verilog language 74ls138 based on the realization of
Platform: | Size: 350208 | Author: 曹旭 | Hits:

[VHDL-FPGA-Verilog] GAL16V8(fangzhen74LS138)

Description: GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时，对简化走线特别有用。简单的修改GAL16V8程序，可灵活地进行地址译码修改。-GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modifications GAL16V8 program, the flexibility to change the address decoding.
Platform: | Size: 2048 | Author: 肖飞 | Hits:

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[Other] 74LS138

[VHDL-FPGA-Verilog] 74hc138

[VHDL-FPGA-Verilog] GAL16V8(fangzhen74LS138)

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