Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop hardware design
Title: DHT11 Download
  • Category:
  • HardWare Design
  • Tags:
  • File Size:
  • 203kb
  • Update:
  • 2018-07-18
  • Downloads:
  • 0 Times
  • Uploaded by:
  • 瑞星
 Description: FPGA Verilog DHT11 temperature and humidity sensor code
 Downloaders recently: [More information of uploader 瑞星]
 To Search:
File list (Check if you may need any files): 
FilenameSizeDate
DHT11\async_send.v 3718  2012-09-26

DHT11\db 0  2018-07-07

DHT11\db\DHT11.db_info 140  2018-07-07

DHT11\db\DHT11.ipinfo 163  2018-07-07

DHT11\db\DHT11.sld_design_entry.sci 202  2018-07-07

DHT11\db\logic_util_heursitic.dat 18436  2012-09-29

DHT11\db\prev_cmp_DHT11.qmsg 44326  2012-09-29

DHT11\DHT11.asm.rpt 7673  2012-09-29

DHT11\DHT11.cdf 333  2012-09-29

DHT11\DHT11.done 26  2012-09-29

DHT11\DHT11.eda.rpt 6093  2012-09-29

DHT11\DHT11.fit.rpt 133345  2012-09-29

DHT11\DHT11.fit.summary 607  2012-09-29

DHT11\DHT11.flow.rpt 9650  2012-09-29

DHT11\DHT11.jdi 315  2012-09-29

DHT11\DHT11.map.rpt 37471  2012-09-29

DHT11\DHT11.map.summary 471  2012-09-29

DHT11\DHT11.pin 27109  2012-09-29

DHT11\DHT11.pof 524506  2012-09-29

DHT11\DHT11.qpf 1292  2012-09-26

DHT11\DHT11.qsf 4262  2018-07-07

DHT11\DHT11.qws 1994  2018-07-07

DHT11\DHT11.sof 151072  2012-09-29

DHT11\DHT11.sta.rpt 129358  2012-09-29

DHT11\DHT11.sta.summary 648  2012-09-29

DHT11\DHT11.v.bak 5676  2012-09-26

DHT11\DHT11_assignment_defaults.qdf 57448  2018-07-07

DHT11\DHT11_cmd.v 2188  2012-09-29

DHT11\DHT11_cmd.v.bak 243  2012-09-26

DHT11\DHT11_nativelink_simulation.rpt 1003  2012-09-26

DHT11\DHT11_opera.v 5716  2018-07-07

DHT11\DHT11_opera.v.bak 5764  2012-09-26

DHT11\DHT11_top.v 2663  2012-09-29

DHT11\DHT11_top.v.bak 286  2012-09-26

DHT11\incremental_db 0  2018-07-07

DHT11\incremental_db\compiled_partitions 0  2018-07-07

DHT11\incremental_db\compiled_partitions\DHT11.db_info 140  2018-07-07

DHT11\incremental_db\compiled_partitions\DHT11.root_partition.cmp.dfp 33  2012-09-29

DHT11\incremental_db\compiled_partitions\DHT11.root_partition.cmp.kpt 217  2012-09-29

DHT11\incremental_db\compiled_partitions\DHT11.root_partition.cmp.logdb 4  2012-09-29

DHT11\incremental_db\compiled_partitions\DHT11.root_partition.map.dpi 980  2012-09-29

DHT11\incremental_db\compiled_partitions\DHT11.root_partition.map.kpt 6635  2012-09-29

DHT11\incremental_db\README 653  2012-09-26

DHT11\simulation 0  2018-07-07

DHT11\simulation\modelsim 0  2018-07-07

DHT11\simulation\modelsim\DHT11.sft 164  2012-09-29

DHT11\simulation\modelsim\DHT11.v 3627  2012-09-26

DHT11\simulation\modelsim\DHT11.vo 271194  2012-09-29

DHT11\simulation\modelsim\DHT11_fast.vo 271199  2012-09-29

DHT11\simulation\modelsim\DHT11_modelsim.xrf 42637  2012-09-29

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak 581  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak1 581  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak2 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak3 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak4 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak5 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak6 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak7 588  2012-09-26

DHT11\simulation\modelsim\DHT11_run_msim_rtl_verilog.do.bak8 588  2012-09-26

DHT11\simulation\modelsim\DHT11_v.sdo 209129  2012-09-29

DHT11\simulation\modelsim\DHT11_v_fast.sdo 203258  2012-09-29

DHT11\simulation\modelsim\modelsim.ini 11083  2012-09-26

DHT11\simulation\modelsim\msim_transcript 2958  2012-09-26

DHT11\simulation\modelsim\my.do 478  2012-09-26

DHT11\simulation\modelsim\rtl_work 0  2018-07-07

DHT11\simulation\modelsim\rtl_work\@d@h@t11 0  2018-07-07

DHT11\simulation\modelsim\rtl_work\@d@h@t11\_primary.dat 1905  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11\_primary.dbs 3387  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11\_primary.vhd 384  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11\verilog.prw 4926  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11\verilog.psm 24096  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst 0  2018-07-07

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst\_primary.dat 1729  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst\_primary.dbs 3317  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst\_primary.vhd 237  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst\verilog.prw 3324  2012-09-26

DHT11\simulation\modelsim\rtl_work\@d@h@t11_vlg_tst\verilog.psm 14832  2012-09-26

DHT11\simulation\modelsim\rtl_work\_info 775  2012-09-26

DHT11\simulation\modelsim\rtl_work\_temp 0  2012-09-29

DHT11\simulation\modelsim\rtl_work\_vmake 26  2012-09-26

DHT11\simulation\modelsim\vsim.wlf 57344  2012-09-26

CodeBus www.codebus.net