- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 420kb
- Update:
- 2018-04-21
- Downloads:
- 0 Times
- Uploaded by:
- 硅渣渣
Description: The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an internal output clock, that is, let FX2 give our design as the clock source, and output a clock with the largest configuration clock 48M.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| FPGA_USB2.0设计.docx | 433049 | 2017-07-09 |
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