Description: verilog example Code routines, it is mainly used for the verilog HDL language beginners to learn
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| lab4 | 0 | 2017-04-17
|
| lab4\hdl_lab4.doc | 85727 | 2017-04-16
|
| lab4\wire_reg数据类型.doc | 14848 | 2017-04-16
|
| lab4\第二弹.ppt | 804864 | 2017-04-16 |
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