Title:
ef48dc75a9a60030c622898a19b0f2d6 (1)
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- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 15kb
- Update:
- 2017-12-31
- Downloads:
- 0 Times
- Uploaded by:
- 刘昱杉
Description: There is a program language on the encoder of the loop code, which can be opened with Quartus II
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 循环码编码器verilog实现\循环码编码器\1.bmp | 1073718 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器\2.bmp | 1066038 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器\crc_3.txt | 3108 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器\crc_3_testbench.txt | 846 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器\crc_3.v | 2970 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器\crc_3_test.v | 806 | 2008-02-17
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| 循环码编码器verilog实现\循环码编码器 | 0 | 2008-03-02
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| 循环码编码器verilog实现 | 0 | 2008-03-02
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| readme_verysource.com.txt | 221 | 2013-07-17 |
