- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 23kb
- Update:
- 2017-12-31
- Downloads:
- 0 Times
- Uploaded by:
- 刘昱杉
Description: This is a coding that can implement frame synchronization, using Verilog coding
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| frame_sync\work\_info | 470 | 2006-03-20
|
| frame_sync\work\frame\_primary.vhd | 400 | 2006-03-20
|
| frame_sync\work\frame\verilog.asm | 16837 | 2006-03-20
|
| frame_sync\work\frame\_primary.dat | 1488 | 2006-03-20
|
| frame_sync\work\frame | 0 | 2006-03-20
|
| frame_sync\work\test_frame\_primary.vhd | 80 | 2006-03-20
|
| frame_sync\work\test_frame\verilog.asm | 17874 | 2006-03-20
|
| frame_sync\work\test_frame\_primary.dat | 2975 | 2006-03-20
|
| frame_sync\work\test_frame | 0 | 2006-03-20
|
| frame_sync\work | 0 | 2006-03-20
|
| frame_sync\frame.v | 1969 | 2006-03-20
|
| frame_sync\test_frame.v | 3704 | 2006-03-20
|
| frame_sync\vsim.wlf | 32768 | 2006-03-20
|
| frame_sync\frame.mpf | 17054 | 2006-03-20
|
| frame_sync\frame.cr.mti | 545 | 2006-03-20
|
| frame_sync\transcript | 493 | 2006-03-21
|
| frame_sync | 0 | 2006-03-19 |
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