MIPS_CPU-master
...............\.gitignore
...............\ALU.v
...............\BranchControl.v
...............\EX.v
...............\EX_MEM.v
...............\ForwardControl.v
...............\HazardControl.v
...............\ID.v
...............\ID_EX.v
...............\IF.v
...............\IF_ID.v
...............\LICENSE
...............\MEM.v
...............\MEM_WB.v
...............\README.md
...............\RM_ctrl.v
...............\WM_ctrl.v
...............\decoder.v
...............\define.v
...............\doc
...............\...\Five-Stage MIPS Pipeline in Verilog HDL.pdf
...............\...\Five-Stage MIPS Pipeline in Verilog HDL.tex
...............\...\Instructions.pdf
...............\...\blueprint.pdf
...............\...\branch.png
...............\...\cpu.bib
...............\hilo_reg.v
...............\pipeline_CPU.v
...............\regfile.v
...............\testBenches
...............\...........\IF_tb.v
...............\...........\SOPC.v
...............\...........\dffe_tb.v
...............\...........\hilo_reg_tb.v
...............\...........\memory.v
...............\...........\memory_tb.v
...............\...........\mux2x1_tb.v
...............\...........\mux4x1_tb.v
...............\...........\regfile_tb.v
...............\...........\rom.v
...............\...........\rom_tb.v
...............\...........\testData
...............\...........\........\branch_in.data
...............\...........\........\converter.java
...............\...........\........\data.data
...............\...........\........\data_gen.java
...............\...........\test_info
...............\...........\.........\arithmetic
...............\...........\.........\..........\SOPC.v
...............\...........\.........\..........\arithmetic.data
...............\...........\.........\..........\arithmetic.png
...............\...........\.........\..........\arithmetic.s
...............\...........\.........\..........\arithmetic_div.data
...............\...........\.........\..........\arithmetic_div.png
...............\...........\.........\..........\arithmetic_div.s
...............\...........\.........\bitwise
...............\...........\.........\.......\SOPC.v
...............\...........\.........\.......\bitwise.data
...............\...........\.........\.......\bitwise.png
...............\...........\.........\.......\bitwise.s
...............\...........\.........\branch
...............\...........\.........\......\branch.data
...............\...........\.........\......\branch.png
...............\...........\.........\......\branch.s
...............\...........\.........\dependency (forwarding)
...............\...........\.........\.......................\SOPC.v
...............\...........\.........\.......................\dependency.data
...............\...........\.........\.......................\dependency.png
...............\...........\.........\.......................\dependency.s
...............\...........\.........\logic
...............\...........\.........\.....\SOPC.v
...............\...........\.........\.....\logic.data
...............\...........\.........\.....\logic.png
...............\...........\.........\.....\logic.s
...............\...........\.........\memory
...............\...........\.........\......\SOPC.v
...............\...........\.........\......\memory.data
...............\...........\.........\......\memory.png
...............\...........\.........\......\memory.s
...............\...........\.........\pipeline_basis
...............\...........\.........\..............\SOPC.v
...............\...........\.........\..............\basis.data
...............\...........\.........\..............\pipeline_basis.s
...............\...........\.........\..............\vcd.png
...............\...........\.........\yamin
...............\...........\.........\.....\ram.data
...............\...........\.........\.....\yamin.data
...............\...........\.........\.....\yamin1.s
...............\utilities
...............\.........\dffe.v
...............\.........\mux2x1.v
...............\.........\mux4x1.v