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Title: digital_clock Download
 Description: Vivado based on the FPGA digital alarm clock procedures, verilog language
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digital_clock\design_source\bcd_counter.v
.............\.............\binbcd8.v
.............\.............\clk_1s.v
.............\.............\counter.v
.............\.............\count_top.v
.............\.............\display.v
.............\.............\seg7.v
.............\xdc\clock.xdc
.............\design_source
.............\xdc
digital_clock

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