- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 623kb
- Update:
- 2017-12-11
- Downloads:
- 0 Times
- Uploaded by:
- 高文旭
Description: Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.
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| Filename | Size | Date |
|---|
| Verilog秒表设计.doc | 775168 | 2017-12-11 |
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