- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 7.03mb
- Update:
- 2017-12-07
- Downloads:
- 0 Times
- Uploaded by:
- 史自牧
Description: Serial port controller
To Search:
File list (Check if you may need any files):
Filename | Size | Date |
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lab5
|
lab5\APP
|
lab5\APP\serial_port_utility_latest.exe | 7447240 | 2016-05-18
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lab5\H2L_detect.v | 326 | 2016-11-15
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lab5\L2H_detect.v | 326 | 2016-11-15
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lab5\btn_debounce.v | 791 | 2016-11-15
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lab5\code_ctl.v | 1313 | 2016-11-15
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lab5\data_show.v | 1169 | 2016-11-15
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lab5\delay_10ms.v | 939 | 2016-11-15
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lab5\input_signal_processing.v | 1424 | 2016-11-15
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lab5\meta_harden.v | 405 | 2016-11-15
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lab5\number_encode.v | 1918 | 2016-11-15
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lab5\out_ctl.v | 304 | 2016-11-15
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lab5\reverse_detect.v | 345 | 2016-11-15
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lab5\rx_band_gen.v | 883 | 2016-11-15
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lab5\rx_ctl.v | 2082 | 2016-11-15
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lab5\rx_top.v | 762 | 2016-11-15
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lab5\scan_data.v | 1497 | 2016-11-15
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lab5\sim
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lab5\sim\uart_top_tb.v | 2755 | 2016-11-15
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lab5\tx_band_gen.v | 843 | 2016-11-15
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lab5\tx_ctl.v | 2016 | 2016-11-15
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lab5\tx_top.v | 660 | 2016-11-15
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lab5\uart_demo.v | 1626 | 2016-11-15
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lab5\uart_top.v | 2289 | 2016-12-12
|
lab5\xdc
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lab5\xdc\uart.xdc | 3157 | 2016-12-12 |