- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 30kb
- Update:
- 2017-12-04
- Downloads:
- 0 Times
- Uploaded by:
- 孙小小
Description: A square wave generation circuit is designed, and function verification and time series verification are carried out.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 流程图.jpg | 51843 | 2017-06-19
|
| fangbo.v | 734 | 2017-06-19
|
| fangbo.v.bak | 731 | 2017-06-19
|
| fangbo_tb.v | 217 | 2017-06-18
|
| fangbo_tb.v.bak | 217 | 2017-03-31 |
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