Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: pluse_count Download
  • Category:
  • VHDL-FPGA-Verilog
  • Tags:
  • File Size:
  • 1kb
  • Update:
  • 2017-02-24
  • Downloads:
  • 0 Times
  • Uploaded by:
  • KO
 Description: To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly
 Downloaders recently: [More information of uploader KO]
 To Search:
File list (Check if you may need any files): 
 

pluse_count.vhd

CodeBus www.codebus.net