Title:
Graphics-and-mixed-VHDL-input
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- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 163kb
- Update:
- 2016-06-02
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- Uploaded by:
- 漆广文
Description: Circuit design, graphics, and mixed VHDL input
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Graphics and mixed VHDL input\example6\exp3.bsf
.............................\........\exp3.vhd
.............................\........\exp4.bsf
.............................\........\exp4.vhd
.............................\........\exp5.bsf
.............................\........\exp5.vhd
.............................\........\exp6.asm.rpt
.............................\........\exp6.bdf
.............................\........\exp6.done
.............................\........\exp6.eda.rpt
.............................\........\exp6.fit.eqn
.............................\........\exp6.fit.rpt
.............................\........\exp6.fit.smsg
.............................\........\exp6.fit.summary
.............................\........\exp6.flow.rpt
.............................\........\exp6.map.eqn
.............................\........\exp6.map.rpt
.............................\........\exp6.map.summary
.............................\........\exp6.pin
.............................\........\exp6.pof
.............................\........\exp6.qpf
.............................\........\exp6.qsf
.............................\........\exp6.qws
.............................\........\exp6.sof
.............................\........\exp6.sta.rpt
.............................\........\exp6.sta.summary
.............................\........\exp6.tan.rpt
.............................\........\exp6.tan.summary
.............................\........\exp6_assignment_defaults.qdf
.............................\........\incremental_db\compiled_partitions\exp6.root_partition.map.kpt
.............................\........\..............\README
.............................\........\simulation\modelsim\exp6.sft
.............................\........\..........\........\exp6.vho
.............................\........\..........\........\exp6_8_1200mv_0c_vhd_slow.sdo
.............................\........\..........\........\exp6_8_1200mv_85c_vhd_slow.sdo
.............................\........\..........\........\exp6_min_1200mv_0c_vhd_fast.sdo
.............................\........\..........\........\exp6_modelsim.xrf
.............................\........\..........\........\exp6_vhd.sdo
.............................\........\timing\custom\exp6.vho
.............................\........\......\......\exp6_vhd.sdo
.............................\........\......\primetime\exp6.vho
.............................\........\......\.........\exp6_pt_vhd.tcl
.............................\........\......\.........\exp6_vhd.sdo
.............................\Graphics and mixed VHDL input.docx
.............................\example6\incremental_db\compiled_partitions
.............................\........\simulation\modelsim
.............................\........\timing\custom
.............................\........\......\primetime
.............................\........\db
.............................\........\incremental_db
.............................\........\simulation
.............................\........\timing
.............................\example6
Graphics and mixed VHDL input
