- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2015-02-18
- Downloads:
- 0 Times
- Uploaded by:
- sam
Description: We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a simple test bench code must be written to apply a sequence of inputs (Stimulators) to the circuit being tested (UUT). The output of the test bench and UUT interaction can be observed in the simulation waveform window.
To Search:
File list (Check if you may need any files):
COMB.VHD
Download