NSN-day1\labs
........\....\1-setup
........\....\.......\.solutions
........\....\.......\..........\setup_1_vhdl_arbiter
........\....\.......\..........\....................\arbiter.vhd
........\....\.......\..........\....................\setup.tcl
........\....\.......\..........\setup_2_vhdl_w_hierarchy
........\....\.......\..........\........................\cells.vhd
........\....\.......\..........\........................\cfg_reg.vhd
........\....\.......\..........\........................\dff.vhd
........\....\.......\..........\........................\projectpack.vhd
........\....\.......\..........\........................\reg.vhd
........\....\.......\..........\........................\setup.tcl
........\....\.......\..........\setup_3_verilog_arbiter
........\....\.......\..........\.......................\arbiter.v
........\....\.......\..........\.......................\setup.tcl
........\....\.......\..........\setup_4_verilog_w_libraries
........\....\.......\..........\...........................\design.flist
........\....\.......\..........\...........................\include
........\....\.......\..........\...........................\.......\.svn
........\....\.......\..........\...........................\.......\....\entries
........\....\.......\..........\...........................\.......\....\prop-base
........\....\.......\..........\...........................\.......\....\props
........\....\.......\..........\...........................\.......\....\text-base
........\....\.......\..........\...........................\.......\....\.........\projectpack.v.svn-base
........\....\.......\..........\...........................\.......\....\tmp
........\....\.......\..........\...........................\.......\....\...\prop-base
........\....\.......\..........\...........................\.......\....\...\props
........\....\.......\..........\...........................\.......\....\...\text-base
........\....\.......\..........\...........................\.......\projectpack.v
........\....\.......\..........\...........................\mylib.v
........\....\.......\..........\...........................\reg.v
........\....\.......\..........\...........................\setup.tcl
........\....\.......\..........\...........................\setup_vlog.tcl
........\....\.......\..........\...........................\tsbvlib
........\....\.......\..........\...........................\.......\dff.tsbvlib
........\....\.......\..........\...........................\.......\reg4.tsbvlib
........\....\.......\..........\setup_5_wb_dma
........\....\.......\..........\..............\rtl
........\....\.......\..........\..............\...\verilog
........\....\.......\..........\..............\...\.......\.svn
........\....\.......\..........\..............\...\.......\....\entries
........\....\.......\..........\..............\...\.......\....\prop-base
........\....\.......\..........\..............\...\.......\....\props
........\....\.......\..........\..............\...\.......\....\text-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_ch_arb.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_ch_pri_enc.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_ch_rf.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_ch_sel.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_de.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_defines.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_inc30r.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_pri_enc_sub.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_rf.v.svn-base
........\....\.......\..........\..............\...\.......\....\.........\wb_dma_top.v.svn-base
........\.