Description: In this work, we present a chaos based integrated
jitter booster circuit for use in multiple oscillator sampling true
random number generator architecture. Multiple ring oscillator
based true random number generators need significant number
of rings for accumulating the intrinsic jitter of inverters to a
useful level. Thus, they occupy large silicon area and consume
considerable amount of power. The proposed circuit offers
an alternative approach for boosting jitter using the chaotic
dynamics generated by non-linear coupling of two ring oscillators
that require fewer number of components. The simplicity of the
proposed circuit offers high integration potential with inherent
low area and power consumption advantages. Chaotic dynamics
of the circuit was studied using both numerical and circuit
simulations. Measurement results of the test chip implemented at
250nm CMOS technology node confirmed chaotic behavior and
jitter boosting capability. To the very best of our knowled
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