Description: A novel approach to equalization of high-speed serial
links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters
in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1
output multiplexer.
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Pre Emphasis\20140714181903985025.pdf
............\buckwalter2006.pdf
............\kern2007.pdf
............\oe-15-2-430.pdf
............\zhang2005.pdf
Pre Emphasis
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